Hi,

I found this simple, controlled battery monitor circuit online. However, I'm trying to better understand how this works and if I can make it better, by changing the resistor values. I want to monitor the voltage on a 3.7V(Nominal Voltage) Li-Po Battery, and I was wondering what the 100K resistor (R3) is for and the affects of changing the 2K resistor (R4) to something bigger for example 10K?

Thanks in advance for your help!

 

The circuit is simply a switch to turn the battery voltage on and off to the "To ADC BATTSENS" output for measuring by an A/D converter.
The 100k resistor R3 is simply to provide OFF bias to Q1.
R4 could be changed to 10k , depending upon the input control voltage.
R1 and R2 are voltage dividers to reduce the maximum voltage to the ADC.

 

Q1 is a p-channel mosfet. So the 100k is used to bias Q1 on when Q2 switches on under the control of the battery sense enable signal.

 

Thanks for the quick responses!

So if the 100k resistor is used for biasing would C1 be necessary? Or is C1 used for another purpose?

 

C1 is only necessary if there is RF around (like inside a cell phone).

 

Do note for this circuit to work there must be a stable voltage reference below the expected range of the battery.

Why? You need a reference for comparison for the A2D converter. If you try using the battery voltage itself as the reference you will eventually find out the divided down battery voltage and the battery voltage itself both vary by the same ratio, and that ratio is the resistor ratio.

Thus you need a fixed point for a true comparison.

Myself, I would change Q2 to an N channel MOSFET and ditch C1 and R4.

 

Thanks Ernie.

I was wondering if I were to switch to an N channel Mosfet, would I have to consider the biasing of Q2?

 

Thanks Ernie.

I was wondering if I were to switch to an N channel Mosfet, would I have to consider the biasing of Q2?

I think you misunderstood Ernie. Q2 (originally an NPN bipolar) is to be replaced with an NFET. The main switch Q1 remains a PFET.

 

Thanks Mike.

However, I just want to be clear, does that mean we would not need to worry about any biasing on the NFET and only the PFET?

 

Thanks Mike.

However, I just want to be clear, does that mean we would not need to worry about any biasing on the NFET and only the PFET?

Since the gate of the (new) NFET is driven directly from a MCU port pin, as long as the NFET is a "logic-level-gate" device, then no other biasing is necessary. The only "biasing" requirement is that R3 pulls the gate of Q1 to a state that properly turns it off when the NFET is turned off. The NFET has to sink the current sourced by R3 to turn on Q1.