Basic: MOSFET negative gate voltage rating question

Thread Starter

Mot93

Joined Apr 9, 2016
10
Hello,

So I have this IRFP7537, I want to use a +- voltage to drive it on a half bridge.
Now the maximum gate voltage rating is +-20V, the driver outputs a +20 top and a -5V bottom signal.
1) Will this FET tolerate this voltages or is it strictly the +20Volts or -20v?
2) In case of being too much voltage, will a TVS diode like SA18CA protect it?

Other data:
VDS=400V
fs=10kHz

upload_2018-2-6_20-18-47.png
 

#12

Joined Nov 30, 2010
18,190
Theoretically, the mosfet will survive but a good designer never dances on the edge of the rating. Better to put a resistor between the driver and the gate, then a zener to ground of somewhere between 10V and 16V...in my opinion, and if the frequency requirements will allow a resistor.
 

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Aleph(0)

Joined Mar 14, 2015
597
the driver outputs a +20 top and a -5V bottom signal.
Mot93 I understand what you're trying to do but you're confusing absolute maximum stress with design maximum stress which in practice means your circuit will be unreliable with unacceptably low MTBF:(

So just as example I limit Vgs excursion of IRFP260s (which also have absolute max Vgs spec of ±20V) in my full bridge 80kHz current mode PWM switch to 15V. Now in theory any Vgs > 10V will saturate device for all intents and purposes but at _high_ frequencies (which includes rapid transient times) _LPF action_ of inter-electrode capacitance can necessitate greater drive voltage. So you'll prolly be fine at 10kHz as long as rise time isn't extremely stringent but I definitely suggest active driver design for freqs and applications requiring driver outputs >15V:)!

So sry if saying _inter-electrode_ instead of _junction_ seems strange but I needed to include gate which isn't really a junction;)

PS, just in case #12 sees this, FWIW I definitely like your post but I'd be breaking promise to avoid tagging you if I _liked_ it:(o_O
 

MrAl

Joined Jun 17, 2014
7,194
Hi,

I would stay away from the +20v signal because that is the absolute max rating.
You could check the data sheet, but i think +10v turns on the mosfet all the way if i remember right. That means anything above that just makes it take longer to turn off with a given drive current. If you must, then +12v or something like that, but never +20v.
The -5v signal should be well within the bottom range limit but that voltage is most likely by default of the driver.
 

Thread Starter

Mot93

Joined Apr 9, 2016
10
Theoretically, the mosfet will survive but a good designer never dances on the edge of the rating. Better to put a resistor between the driver and the gate, then a zener to ground of somewhere between 10V and 16V...in my opinion, and if the frequency requirements will allow a resistor.
Ok hehe, I usually don't get to the maximum values, this time I'm trying to get a different way on driving MOSFETs, I always use 0 to 12V and 0 to 15 V.

Thank you for the zener tip
 

Thread Starter

Mot93

Joined Apr 9, 2016
10
Mot93 I understand what you're trying to do but you're confusing absolute maximum stress with design maximum stress which in practice means your circuit will be unreliable with unacceptably low MTBF:( "
Yes that's what I thought :) !!

"So just as example I limit Vgs excursion of IRFP260s (which also have absolute max Vgs spec of ±20V) in my full bridge 80kHz current mode PWM switch to 15V. Now in theory any Vgs > 10V will saturate device for all intents and purposes but at _high_ frequencies (which includes rapid transient times) _LPF action_ of inter-electrode capacitance can necessitate greater drive voltage. So you'll prolly be fine at 10kHz as long as rise time isn't extremely stringent but I definitely suggest active driver design for freqs and applications requiring driver outputs >15V:)!

So sry if saying _inter-electrode_ instead of _junction_ seems strange but I needed to include gate which isn't really a junction;)"
I actually plan on going higher on frequency but that rings some bells, I've read it before :)!!

PS, just in case #12 sees this, FWIW I definitely like your post but I'd be breaking promise to avoid tagging you if I _liked_ it:(o_O
No problem, from what I read on your reply you do have vast knowledge on the topic ;)
And I really found this helpful for my tests, because I'm gonna be using higher currents and other devices in the near future.

Thanks a lot
 

Thread Starter

Mot93

Joined Apr 9, 2016
10
Hi,

I would stay away from the +20v signal because that is the absolute max rating.
You could check the data sheet, but i think +10v turns on the mosfet all the way if i remember right. That means anything above that just makes it take longer to turn off with a given drive current. If you must, then +12v or something like that, but never +20v.
The -5v signal should be well within the bottom range limit but that voltage is most likely by default of the driver.
Thank you!
 

MrAl

Joined Jun 17, 2014
7,194
MrAl it's not quite that simple especially with increasing freqs/transition times! I tried to explain that in post 3 sry if it wasn't clear:(

@Aleph(0)

Hi,

Not sure what you mean here. Are you saying that the MOSFET will not be turned on all the way with +10 volts?
To get higher frequency switching we need higher drive current, not necessarily higher drive voltage.
 

Aleph(0)

Joined Mar 14, 2015
597
Not sure what you mean here. Are you saying that the MOSFET will not be turned on all the way with +10 volts?
MrAl So practically speaking 12V basically guarantees saturation and, o/c, like you're saying, R[on] is specified at 10V:) But it gets more _complicated_ with increasing Freqs/steeper transition times, not cuz of any increase in Vgs[sat] (which there isn't) but cuz of interference with drive signal caused by inter-electrode reactance (so for example lead/lag, attenuation and like that).

To get higher frequency switching we need higher drive current, not necessarily higher drive voltage.
MrAl I totally agree! But I also say increasing peak Vgs excursion can be means to that end:)! Now just so you know, I'm definitely NOT a big fan of expediency! Also I'd never advise excess of 17 volts under any circumstance! But kept within that limit it can simplify driver output topology down to just direct-coupled active _totem pole_ which has advantage of super-wide frequency agility (w/o sacrificing reliability of fets)! Which is vry accommodating to applications where maintenance of stringent transient times is important:cool:! It also has vry welcome _side effect_ of easing design of _charge pump{s}_ for high-side gate{s}:)
 

Aleph(0)

Joined Mar 14, 2015
597
PS, just in case #12 sees this, FWIW I definitely like your post but I'd be breaking promise to avoid tagging you if I _liked_ it:(o_O
@Mot93 Since it looks like I caused some confusion:oops: This is to clarify that the above quoted paragraph was NOT directed toward you in any way:)! It's just my _nod_ to post 2 with explanation that my failure to _up vote_ it was strictly at its author's (#12's) request (which is agreement strictly between he and I!) So he welcomes _likes_ from other ppl:cool:!

Sry for confusion:oops:
 

MrAl

Joined Jun 17, 2014
7,194
MrAl So practically speaking 12V basically guarantees saturation and, o/c, like you're saying, R[on] is specified at 10V:) But it gets more _complicated_ with increasing Freqs/steeper transition times, not cuz of any increase in Vgs[sat] (which there isn't) but cuz of interference with drive signal caused by inter-electrode reactance (so for example lead/lag, attenuation and like that).


MrAl I totally agree! But I also say increasing peak Vgs excursion can be means to that end:)! Now just so you know, I'm definitely NOT a big fan of expediency! Also I'd never advise excess of 17 volts under any circumstance! But kept within that limit it can simplify driver output topology down to just direct-coupled active _totem pole_ which has advantage of super-wide frequency agility (w/o sacrificing reliability of fets)! Which is vry accommodating to applications where maintenance of stringent transient times is important:cool:! It also has vry welcome _side effect_ of easing design of _charge pump{s}_ for high-side gate{s}:)

Hello again,

Well, i am stating that 12v turns it on (probably 10v, but lets make sure).
I can say that i believe because that 12v is a static specification, not dynamic. That's after all transients have settled, and that is the usual way to spec that.

However, if you want to get into the dynamics, then you would really have to show what happens BEFORE we reach that 12v (assuming gate to source). If you quote inter electrode elements then we only have three, one is parallel capacitance, the other is series inductance, and the other is series resistance.
The capacitance is charged via a current, so if we specify a current we get past that one. That leaves us with series resistance and inductance.

Most likely the series resistance will be very small in comparison to the internal series resistance, so let's give that a break for now.
That leaves us with the series inductance.

The series inductance is known to cause problems, namely, the oscillations from the source series inductance which causes what looks like feedback which causes the Vgs to vary as the MOSFET starts to turn on. If we ignore the oscillations for now, we are left with the inductance di/dt.

The di/dt in the source inductance goes up with increased voltage. That would imply that we get a higher current in a shorter period of time and thus turn on faster. So if the response was overdamped, we would get a faster turn on.

I agree with that fully and we see this in other applications too not just mosfets, but i would have to caution that a fast turn on with significant inductance to cause a need for a higher voltage could just bypass the mechanisms put in place to circumvent the oscillation problems.
In other words, when we use a series resistor we are trying to limit di/dt anyway, and if we go higher in gate drive voltage we just end up having to increase the value of the series resistor.

So yes, increasing the drive voltage could increase the turn on time or it could lead to more oscillations. So i agree with you in part but we would have to look at a specific circuit to understand if we should do this or not.

The other point is that we usually specify a driver that is capable of some amperage (like 1 amp or whatever). We often assume we get that during charge/discharge of the gate. According to your statements you imply that we should not assume that, and that's a good point i think.
Originally though i was just taking statics, but i am happy you brought the dynamics into the picture too.

I have a feeling your points were more toward addressing the problems with the external resistances and inductances but no big deal i guess. If you would like to elaborate that's cool too :)
 

Aleph(0)

Joined Mar 14, 2015
597
Well, i am stating that 12v turns it on (probably 10v, but lets make sure).
I can say that i believe because that 12v is a static specification, not dynamic. That's after all transients have settled, and that is the usual way to spec that.
Emphasis mine
Agreed:)!


However, if you want to get into the dynamics, then you would really have to show what happens BEFORE we reach that 12v (assuming gate to source). If you quote inter electrode elements then we only have three, one is parallel capacitance, the other is series inductance, and the other is series resistance.
The capacitance is charged via a current, so if we specify a current we get past that one. That leaves us with series resistance and inductance.

Most likely the series resistance will be very small in comparison to the internal series resistance, so let's give that a break for now.
That leaves us with the series inductance.

The series inductance is known to cause problems, namely, the oscillations from the source series inductance which causes what looks like feedback which causes the Vgs to vary as the MOSFET starts to turn on. If we ignore the oscillations for now, we are left with the inductance di/dt.
MrAl o/c what you're saying is standard engineering approach/perspective which I have no problem with:cool:! But I feel strong need to add qualification that all ppl should remain cognizant of difference between _modeling tools_ and _cold, scary_ reality (for example the construct of discreet Z elements vs the actuality of distributed impedance) So I say even though embracing (actually in this case more like _leaning toward_) empiricism can be convenient and even practical it's also trading comprehension for just rote _technique_ which I say is a bad road to start down cuz no matter their field of study or expertise sooner or later ppl need to have real picture instead of empirical model! So anyhow that's just my opinion sry for digression but I have like _bee in my bonnet_ on subject of STEM education going too far representing like continuous reality with discrete modelso_O

The di/dt in the source inductance goes up with increased voltage. That would imply that we get a higher current in a shorter period of time and thus turn on faster. So if the response was overdamped, we would get a faster turn on. I agree with that fully and we see this in other applications too not just mosfets, but i would have to caution that a fast turn on with significant inductance to cause a need for a higher voltage could just bypass the mechanisms put in place to circumvent the oscillation problems. In other words, when we use a series resistor we are trying to limit di/dt anyway, and if we go higher in gate drive voltage we just end up having to increase the value of the series resistor.

So yes, increasing the drive voltage could increase the turn on time or it could lead to more oscillations.
MrAl that's exactly why I use active _totem pole_ with artificial _swinging reactance_ to spoil Q:)!

So i agree with you in part but we would have to look at a specific circuit to understand if we should do this or not.
MrAl I totally agree and I hope I didn't give impression that it was universally applicable solution:eek:!

The other point is that we usually specify a driver that is capable of some amperage (like 1 amp or whatever). We often assume we get that during charge/discharge of the gate. According to your statements you imply that we should not assume that
MrAl yes you're correct! IMO it's best to start by just looking on impedances as just impedances (or being more general, entities as just what they are) in their own right, outside of _framing context_ and w/o trying to break them down into ostensibly _more digestible_ bits or dumb them into convenient but totally arbitrary template! So tnx for pointing out something that IMO is major problem with technical literature and even education on subject of insulated gate semiconductors (like MOSFET and IGBT) and even electron tubes! Which is trying to fit 'dynamic peg' into 'static gap':rolleyes: I just wish educators and manufactures would hurry up and figure out that ppl aren't as lazy as they seem to think:rolleyes:! Now o/c I can't speak for anyone but myself but all I'm saying is that ppl should be encouraged to think for themselves! So plz don't get me wrong! Tools (like mental constructs) are totally necessary but they shouldn't be confused with reality (so for vry ugly example think on _holes_ as word is used in semiconductor theory for expedient of representing _positive charge carrier_ as existential entity:confused::rolleyes:!). Also none of my ranting abt empiricism is aimed at you cuz it's totally clear to me you have scientific perspective:)!

Originally though i was just taking statics, but i am happy you brought the dynamics into the picture too.
It's like @Hypatia's Protege says (to paraphrase): _DC Land_ can be a nice place to visit but I wouldn't want to live there;) So I say we couldn't live there even if we wanted tooo_O! So being serious no problem! It's like you said that's how the devices are profiled:)!

i am happy you brought the dynamics into the picture too.
MrAl thanks And I sincerely say THANK YOU! For knowing what you're talking about and having scientific sensibilities:cool:! Which are qualities that just keep getting more and more scarce:(!

If you would like to elaborate that's cool too :)
MrAl w/o giving out too many details before getting into it on Tutorial, you can think on my driver design as basically a _balsy_ TTL output with _swinging negative inductance_ (which is describable from just _swinging capacitance_ only cuz of imperfect analogy:oops::D)
 
Last edited:

MrAl

Joined Jun 17, 2014
7,194
Emphasis mine
Agreed:)!




MrAl o/c what you're saying is standard engineering approach/perspective which I have no problem with:cool:! But I feel strong need to add qualification that all ppl should remain cognizant of difference between _modeling tools_ and _cold, scary_ reality (for example the construct of discreet Z elements vs the actuality of distributed impedance) So I say even though embracing (actually in this case more like _leaning toward_) empiricism can be convenient and even practical it's also trading comprehension for just rote _technique_ which I say is a bad road to start down cuz no matter their field of study or expertise sooner or later ppl need to have real picture instead of empirical model! So anyhow that's just my opinion sry for digression but I have like _bee in my bonnet_ on subject of STEM education going too far representing like continuous reality with discrete modelso_O



MrAl that's exactly why I use active _totem pole_ with artificial _swinging reactance_ to spoil Q:)!


MrAl I totally agree and I hope I didn't give impression that it was universally applicable solution:eek:!


MrAl yes you're correct! IMO it's best to start by just looking on impedances as just impedances (or being more general, entities as just what they are) in their own right, outside of _framing context_ and w/o trying to break them down into ostensibly _more digestible_ bits or dumb them into convenient but totally arbitrary template! So tnx for pointing out something that IMO is major problem with technical literature and even education on subject of insulated gate semiconductors (like MOSFET and IGBT) and even electron tubes! Which is trying to fit 'dynamic peg' into 'static gap':rolleyes: I just wish educators and manufactures would hurry up and figure out that ppl aren't as lazy as they seem to think:rolleyes:! Now o/c I can't speak for anyone but myself but all I'm saying is that ppl should be encouraged to think for themselves! So plz don't get me wrong! Tools (like mental constructs) are totally necessary but they shouldn't be confused with reality (so for vry ugly example think on _holes_ as word is used in semiconductor theory for expedient of representing _positive charge carrier_ as existential entity:confused::rolleyes:!). Also none of my ranting abt empiricism is aimed at you cuz it's totally clear to me you have scientific perspective:)!


It's like @Hypatia's Protege says (to paraphrase): _DC Land_ can be a nice place to visit but I wouldn't want to live there;) So I say we couldn't live there even if we wanted tooo_O! So being serious no problem! It's like you said that's how the devices are profiled:)!


MrAl thanks And I sincerely say THANK YOU! For knowing what you're talking about and having scientific sensibilities:cool:! Which are qualities that just keep getting more and more scarce:(!


MrAl w/o giving out too many details before getting into it on Tutorial, you can think on my driver design as basically a _balsy_ TTL output with _swinging negative inductance_ (which is describable from just _swinging capacitance_ only cuz of imperfect analogy:oops::D)

Hello again,

Well i have to say that is an interesting post for sure. I dont really care for poetry mixed with technological issues, but you seem to have found a nice balance. I could quote several passages, but the "DC land" one was prime on target.

So it sounds like your driver design would be one that seeks to maximize the switching speed of the transistor, without too much concern for complexity although i am sure you would try to get to a simple solution if possible. That is of course commendable.
I would only add one additional item (for now) to the list of complexities we've already established :)
That is, switching speed :)
Now i know we've tried to get the fastest time possible, but another goal is to find an optimum switching time. I happened to find this out in the 1980's when working with a converter and trying to reduce parts count. Now i know that "optimum" should sound like "fastest" but for me it was not so. With the output load being a transformer (as well as wire lengths), the inductances presented a problem for the snubber. I am sure you know that the highest kick back comes from a perfect step and so for a perfect step drive (very fast transistor rise and fall) but for a *ramp* the kick back can be significantly lower. Thus it makes sense to force the mosfet into a ramp switch mode rather than a very fast turn on and turn off time. The reduced dv/dt meant that there was less kick back, with the power concern turning more from the snubber to the transistor itself where the transistor would have to dissipate more power. The optimization goal then was to keep the power in the transistor reasonable while still killing most of the spike with the very transistor that was doing the switching. So in this case, the optimum switch rise/fall time was a tradeoff. The good point is that in *slowing down* the mosfet the oscillations due to internal and lead source inductances are not as much of a problem anymore.

What you said about it not being that simple is coming out now, in the the dynamic behavior is quite a system of it's own.

Back in the day IRF had a good technical book out on predicting this stuff. It's been a long time since i went through that though. I would bet it's online now too though.

Nice chatting with you.
 

ian field

Joined Oct 27, 2012
6,539
Hello,

So I have this IRFP7537, I want to use a +- voltage to drive it on a half bridge.
Now the maximum gate voltage rating is +-20V, the driver outputs a +20 top and a -5V bottom signal.
1) Will this FET tolerate this voltages or is it strictly the +20Volts or -20v?
2) In case of being too much voltage, will a TVS diode like SA18CA protect it?

Other data:
VDS=400V
fs=10kHz

View attachment 145340
Generally speaking; there's no rectifying junctions involved, and the oxide layer dielectric strength is the same either way.

Reversing gate drive will have *SOME* depletion effect on the channel and might reduce turn off losses by a small amount - but I have no memory of seeing it mentioned in a published specification. so designing around that is at your own risk.

As VGA modes became more numerous; monitors started growing post SMPSU switchers - some Philips monitors had series pair Zener gate clamps on the MOSFETs. The combination allowed forward drive somewhere in the general direction of 15 - 18V. Reverse drive was clamped somewhere around 6V ish.

18V is a fairly typical gate voltage - but I've seen a paper that suggests they last longer if you aim somewhere around 12 - 15V.
 

Aleph(0)

Joined Mar 14, 2015
597
Hello again,

Well i have to say that is an interesting post for sure. I dont really care for poetry mixed with technological issues, but you seem to have found a nice balance. I could quote several passages, but the "DC land" one was prime on target.

So it sounds like your driver design would be one that seeks to maximize the switching speed of the transistor, without too much concern for complexity although i am sure you would try to get to a simple solution if possible. That is of course commendable.
I would only add one additional item (for now) to the list of complexities we've already established :)
That is, switching speed :)
Now i know we've tried to get the fastest time possible, but another goal is to find an optimum switching time. I happened to find this out in the 1980's when working with a converter and trying to reduce parts count. Now i know that "optimum" should sound like "fastest" but for me it was not so. With the output load being a transformer (as well as wire lengths), the inductances presented a problem for the snubber. I am sure you know that the highest kick back comes from a perfect step and so for a perfect step drive (very fast transistor rise and fall) but for a *ramp* the kick back can be significantly lower. Thus it makes sense to force the mosfet into a ramp switch mode rather than a very fast turn on and turn off time. The reduced dv/dt meant that there was less kick back, with the power concern turning more from the snubber to the transistor itself where the transistor would have to dissipate more power. The optimization goal then was to keep the power in the transistor reasonable while still killing most of the spike with the very transistor that was doing the switching. So in this case, the optimum switch rise/fall time was a tradeoff. The good point is that in *slowing down* the mosfet the oscillations due to internal and lead source inductances are not as much of a problem anymore.

What you said about it not being that simple is coming out now, in the the dynamic behavior is quite a system of it's own.

Back in the day IRF had a good technical book out on predicting this stuff. It's been a long time since i went through that though. I would bet it's online now too though.

Nice chatting with you.
MrAl nice chatting with you too! Like I say, talk with ppl like you who actually think on things instead of just mindlessly _follow the dots_ is always vry interesting and often educational:)!

I dont really care for poetry mixed with technological issues, but you seem to have found a nice balance.
MrAl it's a fair cop:oops:! So I'd use like _exuberance of youth_ as excuse but I've basically worn that pretty thino_O:oops: Now being totally honest I say it's enthusiasm for subject + lack of discipline when I get started on my interests and hobbies that inspires philosophical perspective! @Hypatia's Protege says my problem is I never got past _wonder of world_ but I'm not totally sure that's a minus:confused:? Anyhow just so you know lapses of formality are NOT disrespect for topic at all! In my case it's exactly opposite:cool:! Which isn't excuse just explanation:)!
 

MrAl

Joined Jun 17, 2014
7,194
MrAl nice chatting with you too! Like I say, talk with ppl like you who actually think on things instead of just mindlessly _follow the dots_ is always vry interesting and often educational:)!


MrAl it's a fair cop:oops:! So I'd use like _exuberance of youth_ as excuse but I've basically worn that pretty thino_O:oops: Now being totally honest I say it's enthusiasm for subject + lack of discipline when I get started on my interests and hobbies that inspires philosophical perspective! @Hypatia's Protege says my problem is I never got past _wonder of world_ but I'm not totally sure that's a minus:confused:? Anyhow just so you know lapses of formality are NOT disrespect for topic at all! In my case it's exactly opposite:cool:! Which isn't excuse just explanation:)!
Hi,

Thanks for the reply.

I may have misspoke slightly there too, maybe i should have used the word "colorful" instead of poetic. A little is nice though.
What i noticed in the past is that if the talk gets too colorful then it gets harder to understand what the person is trying to say. But heck, without the human side of things we'd just be like two computers transferring data over the internet, which of course might get boring :)
Then it's also a chance to use what we have learned in our creative writing class (ha ha) :)
 
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