I have always tied unused inputs on an AND gate to low and on a NAND gate tie unused inputs to high.
As I say according to the truth table of the particular gate.
Why would you tie to high on an AND gate? As I see it it does not really matter as long as they are tied low or high, it is just my way of doing it to simplify things.

Look at post #12

 

Ah, I see the confusion now.

Are we talking about unused gates or unused inputs?

 

I have always tied unused inputs on an AND gate to low and on a NAND gate tie unused inputs to high.
As I say according to the truth table of the particular gate.
Why would you tie to high on an AND gate? As I see it it does not really matter as long as they are tied low or high, it is just my way of doing it to simplify things.

So you are saying that if you wanted to AND four signals together and you had a five-input AND gate that you would tie the unused input LO?

 

Bipolar TTL inputs should be tied high to minimize power consumption.

But I see no particular reason to differentiate between types of logic gates as to whether to tie them high or low. If the output ends up high due to this for certain gates I don't see that as a concern.

However note that all inputs should be tied high or low with CMOS gates. Any floating input could allow that gate to drift to somewhere half-way between V+ and ground. This could cause the FETs on that input to both be on and thus drawing current. That's certainly not desired.

 

Ah, I see the confusion now.

Are we talking about unused gates or unused inputs?

Inputs on a unused AND gate is what I am talking about, sorry I am confusing all here.
Be gentle with me I am only new on this forum.

 

So you are saying that if you wanted to AND four signals together and you had a five-input AND gate that you would tie the unused input LO?

What I am talking about is a unused standard 2 input AND gate or OR gate.

 

If you have an unused gate then it doesn't matter what logic level you tie the inputs.
Just make sure all the inputs are tie to logic low or logic high.

 

Bipolar TTL inputs should be tied high to minimize power consumption.

But I see no particular reason to differentiate between types of logic gates as to whether to tie them high or low. If the output ends up high due to this for certain gates I don't see that as a concern.

However note that all inputs should be tied high or low with CMOS gates. Any floating input could allow that gate to drift to somewhere half-way between V+ and ground. This could cause the FETs on that input to both be on and thus drawing current. That's certainly not desired.

Thanks for the information as I am in the middle of making a electronic Snakes and Ladders game, this is a 2 player game and the normal 100 squares on the board.
The reason for discussing the unused gates is that on my digital dices I had to use 3 AND gates so to reset at 6. I tied the inputs of my unused gate to low for both dice circuits as I knew that if they were floating the outputs would be high in TTL.

Apologies if I am confusing all with my explanation.

 

If you have an unused gate then it doesn't matter what logic level you tie the inputs.
Just make sure all the inputs are tie to logic low or logic high.

Thanks, this is why I was trying to explain my way of doing it using the 1st line of the truth table for the AND or OR gate and the last line for the NAND, NOR and XOR gates tying to high for these.

Just simplifies things in my head.

It was my 1st post that started confusing you as I had it badly composed, apologies for that.