# AT91SAM7S Manual TWI Bit Transmission Diagrams Explanation

#### zacharias1

Joined May 23, 2023
3
Suppose the following diagram from page 297 of the AT91SAM7S processor’s manual:

This diagram specifically shows how transmissions are done using TWI. My question is, in TWD, what is transmitted at the indicated position? I mean supposing the green arrow’s time slice at t=c, it is like the diagram shows that at that point two bits are sent. Why doesn’t the diagram show the bit transmissions using ordinary square pulses? What does it try to show by using one additional square pulse?

#### Papabravo

Joined Feb 24, 2006
20,384
The data bit is sampled on the rising edge of TWCK, so there is only 1-bit in the ACK slot. The way the diagram is drawn, means that the TWD line can be either high or low. Either of those two conditions represents a "valid" state. If it was sitting in the middle of those two voltage levels, that would be a bad-bad thing.

So the ACK stands for Acknowledge. It is transmitted by a peripheral device, specifically the one with the transmitted address, if it correctly receives a message. It sends a "positive" acknowledgement by pulling TDA "low". The sender has put his transmitter into a high impedance state at this time and cannot affect the state of TDA. If no peripheral devices have received the message, then the pullup resistor will maintain TDA at a high level. In essence, a peripheral device "sends" a NAK (Negative Acknowledgement) by doing nothing and letting the pullup resistor do the work.

BTW - Just so you know TWI is an alternate name for I2C. There was some "copyright infringement" nonsense from Philips when they invented I2C.

#### zacharias1

Joined May 23, 2023
3
The data bit is sampled on the rising edge of TWCK, so there is only 1-bit in the ACK slot. The way the diagram is drawn, means that the TWD line can be either high or low. Either of those two conditions represents a "valid" state. If it was sitting in the middle of those two voltage levels, that would be a bad-bad thing.

So the ACK stands for Acknowledge. It is transmitted by a peripheral device, specifically the one with the transmitted address, if it correctly receives a message. It sends a "positive" acknowledgement by pulling TDA "low". The sender has put his transmitter into a high impedance state at this time and cannot affect the state of TDA. If no peripheral devices have received the message, then the pullup resistor will maintain TDA at a high level. In essence, a peripheral device "sends" a NAK (Negative Acknowledgement) by doing nothing and letting the pullup resistor do the work.

BTW - Just so you know TWI is an alternate name for I2C. There was some "copyright infringement" nonsense from Philips when they invented I2C.
Thank you!
However, if the master is the I2C receiver, then the former will send an ACK or NACK for "send more data" or "don't send more data" respectively. How can the master indicate if something went wrong if ACK and NACK now have different semantics?

#### Papabravo

Joined Feb 24, 2006
20,384
I don't understand how ACK and NACK can have different semantics. If the master gets an ACK, it can proceed to the next operation. If it gets a NACK (absence of an ACK), then it needs to retry the operation that failed. The master will never indicate that something is wrong unless you program to handle the NACK in different ways. For example, you might retry three time and then trow a fault condition. It is really up to you how you want to handle things.

#### zacharias1

Joined May 23, 2023
3
I don't understand how ACK and NACK can have different semantics. If the master gets an ACK, it can proceed to the next operation. If it gets a NACK (absence of an ACK), then it needs to retry the operation that failed. The master will never indicate that something is wrong unless you program to handle the NACK in different ways. For example, you might retry three time and then trow a fault condition. It is really up to you how you want to handle things.
If the master is the I2C receiver, then all ACKs or NACKs sent will be coming from the master, except for the first byte where the slave address is specified, correct?
But in the end, I think that the point is what you're saying: it all matterns on how the firmware has been programmed to handle ACKs and NACKs, so their semantics depend on the implementation.

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#### Papabravo

Joined Feb 24, 2006
20,384
At different points in a transaction either side can be the transmitter or the receiver. The master is always the party that initiates a transaction by sending a START condition and the one that ends a transmission by sending a STOP condition. The ACK slot is ALWAYS sent by the receiver of a byte. This will always be the peripheral device in the case of the first byte. The remaining bytes depend on the setting of the R/W* (Read/Write*) bit. When you have TWI hardware managing this stuff it is less of a concern.