AT89C51 GPIO Latch

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Chetan_Jadhav

Joined Mar 2, 2017
52
Hi there,
I have just read the theory about internal architecture of 8051 I/O ports.
According to theory P1 to P3 should be HIGH if they are to be used as input ports.Because if PORTS are LOW then the internal mosfet will always hold pin status as low (Refer the attached diagram )and cant be changed ...making it useless as an input port.
so I tried to test this condition, I made Port1 LOW... connected an active HIGH switch to P1.0 pin and read the pin status after pressing switch and found it high.
and now I am pretty much confused about how it is becoming high and how things are going on inside? please help me to understand it.
here is my assembly code. I have also attached the simulation result (I found same results on hardware too) and PORT internal structure.

org 0
mov p1,#0x00 ; PORT 1 intentionally made 00 so internal MOSFET is now active and 'should not' allow PORT pin to be high by switch
REP:
jnb p1.0,$ ;wait here till switch is not pressed (please refer the schematic for connections )
lcall delay
mov a,p1 ;Read PORT1 to Accumulator
mov p2,a ;show contents of accumulator to PORT2()
sjmp REP
delay:
mov r3,#1
XYZ:
mov r1,#255
ABC:
mov r0,#255
djnz r0,$
djnz r1,ABC
djnz r3,XYZ
RET
end
 

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