I have a project that I have to turn in tomorrow. I am having some difficulties. Its my first year at University, I would be really grateful for some help. Here’s the question,

This combination lock has a minimum sequence of four two-bit input symbols as the combination and appears to the user as if it is an asynchronous circuit. Actually, it is a synchronous circuit with a fast clock and synchronization of the user inputs. For a given input combination, the circuit goes to a state and cycles there until the input changes to a new symbol; thus, the combination cannot contain consecutive appearances of the same symbol. The lock is locked by using an asynchronous RESET.

It will be designed in VHDL Schematics.
Thank you very much

 

Hello,

Show us what you have done up-to now.
That way we can see where you need help.

Bertus

 

And describe what you mean by it "appears to the user as if it is an asynchronous circuit". How does the user interact with it? How do you determine that the user has entered a new two-bit symbol?

 

Hello,

Show us what you have done up-to now.
That way we can see where you need help.

Bertus

I thought of having a four signal inputs, each one of them going into 2x1 MUX with themselves which would at the end appear it to be as if its an 8 bit combination, and the output of the MUXs going into four flip-flops, and the output of the flip-flops going into an AND logic gate according to the desired combination. But I just wanted to get some more ideas.

 

What do you mean "going into a 2x1 MUX with themselves"? Can you provide some kind of a schematic (even a sketch done in Paint)?

What are these four inputs? Where are they coming from? What does the user do in order to enter the combination?

 

I have completed the project, thank you very much to all who paid attention. Have a nice day