Astable and Monostable 555 Cascaded for PWM

Thread Starter

jaylenozchin

Joined May 6, 2018
5
Hi all, first time poster. I am having some trouble setting up 2 cascaded 555 timers. The first Stage in Astable mode feeding its output to the trigger of the second stage in Monostable mode.

I am trying to use this as a variable Duty cycle (from <10% to ~95%). I am having trouble simulating this circuit in NI Multisim as it is giving me a glitched sort of output. I am wondering if I am missing something in my circuit and was hoping someone could help.

The intended use is to drive a DC Motor at around 50Hz Frequency and variable duty cycle.
Pictures attached:
 

Attachments

Thread Starter

jaylenozchin

Joined May 6, 2018
5
That's a very low frequency.
Where did you get that requirement?

Here's an adjustable PWM circuit using a single 555 which you might consider:

Thanks for the reply. The spec sheet of the DC Air Compressor motor requires a 50Hz frequency to run the PWM.
I was considering going back to the single 555 PWM. My only concern is will it allow me to vary the duty cycle as much as in the cascaded mode? Also, should one of the diodes in the schematic you shared be reversed for when the Capacitor discharges back to pin 7?
 

crutschow

Joined Mar 14, 2008
24,963
My only concern is will it allow me to vary the duty cycle as much as in the cascaded mode? Also, should one of the diodes in the schematic you shared be reversed for when the Capacitor discharges back to pin 7?
Yes, that circuit won't work.
Here's a correct version:



Here's circuit that goes from 0% to 100% duty-cycle using one LM339 or LM393.
 

Thread Starter

jaylenozchin

Joined May 6, 2018
5
Thank you for the replies. I would like to understand why my original cascaded 555 timers won't work before I decide to go to another design. Any idea why my setup is causing the glitch I showed in the original attachments? I suspect the simulation tool Ni MultiSim might also not be accurate. I calculated all the numbers to achieve my desired 50Hz frequency and make sure the timing is not an issue according to the datasheet of the 555 monostable mode. I am fairly certain the logic is correct but other than the weird glitch I am seeing in the oscilloscope, I don't see a problem.
Any ideas?
 

crutschow

Joined Mar 14, 2008
24,963
Any idea why my setup is causing the glitch I showed in the original attachments?
As long as the 555 trigger input is low, the output stays high.
You need to differentiate the input to the right 555 so that the trigger is only a short negative going pulse as shown below:
 

Thread Starter

jaylenozchin

Joined May 6, 2018
5
As long as the 555 trigger input is low, the output stays high.
You need to differentiate the input to the right 555 so that the trigger is only a short negative going pulse as shown below:
I have calculated my values accordingly. The datasheet specifies: "During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 μs before the end of the timing interval" \

I have calculated my stage 1 values to have a duty cycle ~50% at a frequency of 50Hz. That gives a period of about 20ms. the Variable Resistor I have in stage 2 should allow the timing interval to to return high >10micro seconds before the end of the timing interval as long as it does not exceed ~8200 Ohms.

The falling edge of the output of stage 1 (astable 555) is the trigger for stage 2 (monostable 555) taking into account the 10micro second delay before the next rising edge. All my math works out, my circuit is wired accordingly, and yet I see this weird glitch when attempting to simulate it and it is driving me nuts... Is there anything I am missing with my currently drawn schematic?

Also, what do you mean by: "differentiate the input to the right 555 so that the trigger is only a short negative going pulse as shown below" ?

Thank you again for the help
 

crutschow

Joined Mar 14, 2008
24,963
Which would be the formula for Period and duty cycle calculation for this circuit?
The period is approximately 0.85/R1C1.
The duty-cycle would theoretically be 50% at the 50% pot wiper position, but is skewed since the standard 555 output does not go to the positive supply rail.
My simulation shows the the duty-cycle is ≈56% at the 50% pot setting.

If you used the CMOS version of the 555, whose output goes to the rail, then the duty-cycle would be close to 50% and the 50% pot setting.
The duty-cycle would then be ≈proportional to the pot setting.
 
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