I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus as displayed in the image below.
In the datasheet I have the following pins:
I am quite puzzled about how I can assign the pin "SEG0" and not all the 4 7-segments I have on the board to the schematic design I have because as it can be seen in the circuit diagram I only have 8 out puts for 7-segment LEDs and there are no I/O available for "SEG0".
Any suggestions to solve this problem is highly appreciated.
In the datasheet I have the following pins:
I am quite puzzled about how I can assign the pin "SEG0" and not all the 4 7-segments I have on the board to the schematic design I have because as it can be seen in the circuit diagram I only have 8 out puts for 7-segment LEDs and there are no I/O available for "SEG0".
Any suggestions to solve this problem is highly appreciated.
