Hello,
I am working on a rather slow (1.8432MHz master clock) cpld design. There are 4 clocks that I generate by dividing the master clock by different integers. The divisions are done with synchronous counters, so the edges of each generated clock should be synchronous with the master but delayed by one clock to q time.
Are the resulting clock domains not considered synchronous? Does the data from one domain require synchronization when being used by another even when the clocks are related as I explained?

Thanks,
Jim




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Welcome to AAC!

The divisions are done with synchronous counters, so the edges of each generated clock should be synchronous with the master but delayed by one clock to q time.
Are the resulting clock domains not considered synchronous?

There will be clock skew that you can take steps to mitigate if it will cause problems.

https://en.wikipedia.org/wiki/Clock... skew),of any two clocks is called their skew.