Are clocks obtained by dividing the same master clock synchronous?

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jch4416

Joined Sep 26, 2011
1
Hello,
I am working on a rather slow (1.8432MHz master clock) cpld design. There are 4 clocks that I generate by dividing the master clock by different integers. The divisions are done with synchronous counters, so the edges of each generated clock should be synchronous with the master but delayed by one clock to q time.
Are the resulting clock domains not considered synchronous? Does the data from one domain require synchronization when being used by another even when the clocks are related as I explained?

Thanks,
Jim




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dl324

Joined Mar 30, 2015
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