I'm confused ....

Repairing some Display/Pushbutton boards for Acme iRock 5S and 5B disco lights, there are two driver chips on the board, type 74HC573, designated U1 and U2.

After removing U2, I have discovered that U2 silk-screen says 74HC574, but a 573 was there in its place. U1 silkscreen is 573.

I've looked at the datasheets for both chips, and can see that the 573 has a "Latch Enable" pin, and the 574 has a "Clock" pin.

573 : "When the LATCH ENABLE (LE) pin is HIGH, the Q outputs follow the D inputs. When LE goes LOW, data at the D inputs will be retained at the outputs"

574 : "Data at the D inputs ... are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input."

Output Control is tied to GND on both U1 and U2.

The "Truth Tables" for both types are Identical.

I'm thinking that if both chips are driven by a simple high-going pulse on the LE/CK pins, there is no difference in the way both types of chip will retain the D inputs onto the Q outputs. Would welcome any comments you might have on this.

 

Hello,

Just compare the datasheets.

Bertus

 

If you compare LE and CP two Pins then you will find out that they are complete different, 74HC573 only needs a High level to active the D latch, but 74HC374 needs a Low to High level clock to latch the D Flip-Flop.

74HC573 -- LE 11 latch enable input (active HIGH), 5.2 Pin description on page 4.
74HC574 -- CP 11 clock input (LOW-to-HIGH, edge triggered), 5.2 Pin description on page 3.

 

I did compare the datasheets Bertus, and I have concluded, by scoping the LE/CK pins, that there is nothing special going on, the data does not change during the LE/CK pulses.

So in this case 573 and 574 will be functionally compatible....

 

It all depends on the timing. The 74HC574 latches will only change state on the CP input edge. The 74HC573 latches will change state any time the LE signal is HIGH.

This means that the inputs must be stable as the 574 CP input rises and that after the CP rising edge, nothing that happens on the input pins (D0-D7) will affect the latches.

For the 573, the latches will follow the input pins any time the LE signal is HIGH. Once that signal goes inactive, the last states at the D0-D7 input pins will be latched.

@daba1955, I see you replied as I was writing this. You've got the right idea, as long as the data doesn't change while the CP or LE input is high, both will work the same way.

 

If you compare LE and CP two Pins then you will find out that they are complete different, 74HC573 only needs a High level to active the D latch, but 74HC374 needs a Low to High level clock to latch the D Flip-Flop.

74HC573 -- LE 11 latch enable input (active HIGH), 5.2 Pin description on page 4.
74HC574 -- CP 11 clock input (LOW-to-HIGH, edge triggered), 5.2 Pin description on page 3.

In this case, as I said above, the 573 transfers D to Q while LE is HIGH, making it static on Q when LE goes low. The 574 transfers, and latches the data on Q on the rising edge of CK.

On this simple circuit, since the LE and CK pins are only pulsed HIGH, and the data on the D bus doesn't change while the pulses are high, then it really doesn't matter that the 573 "latches" on the trailing edge of LE, and the 574 "latches" on the leading edge. I have checked the boards in the other fixtures I am repairing, and they all have 573's where a 574 is silk-screened, so I really don't think it's an issue.

 

One thing I didn't mention, is that the LE on U1, and CK (now an LE) on U2 are driven independently from the motherboard, they are not tied together.

U1 drives the 4-digit seven-segment display anodes (via 330R resistors), and U2 drives 4 discrete LEDs, and the 4 common cathodes.

The display cathodes are also connected to 4 pushbuttons, the common of which goes back to the motherboard, so they are obviously reading the pushbuttons sequentially.

 

then it really doesn't matter that the 573 "latches" on the trailing edge of LE, and the 574 "latches" on the leading edge.

They are two different things, LE just needs a static High level voltage, it doesn't needs to be a pulse, but CP needs to be and it is the positive raising edge and stay on High level voltage.

Edit :
Description in one situation like as when the data need to transfer 8 times then LE(573) just stay on High, but CP(574) needs to have 8 clocks to transfer the data from input to output.

 

If the boards have worked as required with the 'wrong' IC in place then clearly, in this instance, either it doesn't matter which of the two ICs is used or the silk screening is wrong.

 

There is a huge difference between a transparent latch and an edge triggered flip-flop. The straight up answer is they are not the same an by interchanging them you are running a huge risk of creating a problem that will be a bear to debug.

 

As you have seen , they have very different functions,
but , as you have also seen, they are pin compatible.

the 74 output only changes on the rising edge of the clock,
which as you have specked out, in your case is as good as the 73 latch,

 

As you have seen , they have very different functions,
but , as you have also seen, they are pin compatible.

the 74 output only changes on the rising edge of the clock,
which as you have specked out, in your case is as good as the 73 latch,

Except if the data changes while the Clock(Latch Enable) is high. The resulting chaos could be very hard to debug.