Help Needed: 74HC574 as Digital/Analog output interface

Discussion in 'General Electronics Chat' started by Samm, May 25, 2010.

  1. Samm

    Thread Starter New Member

    May 25, 2010
    Basically what I need to do is to connect the data bus of MC68HC11F1 (8-bit port) to 74HC574 which is an octal D-type edge-triggered flip-flops with 3-state output.

    The purpose of the flip-flops is to receive digital output from the microcontroller and pass it to an external device.

    My question is, where should the "clock" pin of the flip-flops (74HC574) be connected to?

    MC68HC11F1 is supposed to function in expanded mode. So the data bus is on port C.

    Here are the datasheets:


    On an unrelated question, how to ghost the static RAM located from $2000 to $3FFF in the microcontroller to a range from $6000 to $7FFF?

    Thanks a ton for any info you posted.
    Last edited: May 25, 2010
  2. rjenkins

    AAC Fanatic!

    Nov 6, 2005
    You need to make an 'address decoder' to define an address (or range of addresses) you want your peripheral port to appear.

    My favorite parts for that job are the 74LS138 and 74LS139.

    You need to pick an unused part of the 64K address range of the chip to use for your extra i/o area.

    Starting at A15 and working down, look at what logic levels you need on the address lines to get that range and use appropriate inputs on a '138 so one of the ouputs is activated in 'your' range.

    If you use the fixed enables for the highest order lines, you will end up with each output representing a 1K address space.

    That may be enough, or you can use that as an enable to another 138 with the remaining inputs from that taken from the next address lines down. Each output on that will be active over a 32 byte range.

    You can decode to whatever precision you like, a single byte location if you want.

    Gate your decoded address signal with the E and R/!W lines and that's your control signal for the latch.

    You can of course use the 74HC138, 74ALS138 etc. depending on your speed and power requirements.

    There are many variations on the scheme, if I was building an expanded system with external RAM & ROM I'd have the first '138 set up to decode to 8K blocks of address space, use some blocks for memory then sub-divide one block with further logic for I/O space.