I have to understand the functioning of the boot strap capacitor, i followed the link Bootstrap it was clear till certain stage then ..

The charging part was clear when the lower Mosfet is ON the bootstrap capacitor charges as per VCC(1 - e^{-t/tau}) as it is PWM input, tau = Rboot * Cboot. Now the question is when the top Mosfet is ON there is a statement in the document in the link

Is the above statement wrong since the point Vs is directly connected to DC+ it can have voltage of VDC+ only.
I have verified another document TIBootstrap

The point HB should be VDC+ + VCboot (that is DC bus voltage + Voltage of the boot capacitor). There shall be internal connection between HB and HO, then only the HO the gate voltage will be greater than the source voltage which is HS and the Mosfet will be turned ON. Is my understanding correct?

 

The first section is wrong, Figure 2.2 is correct.

 

I have to understand the functioning of the boot strap capacitor, i followed the link Bootstrap it was clear till certain stage then ..
View attachment 361961
The charging part was clear when the lower Mosfet is ON the bootstrap capacitor charges as per VCC(1 - e^{-t/tau}) as it is PWM input, tau = Rboot * Cboot. Now the question is when the top Mosfet is ON there is a statement in the document in the link
View attachment 361963
Is the above statement wrong since the point Vs is directly connected to DC+ it can have voltage of VDC+ only.
I have verified another document TIBootstrap
View attachment 361962
The point HB should be VDC+ + VCboot (that is DC bus voltage + Voltage of the boot capacitor). There shall be internal connection between HB and HO, then only the HO the gate voltage will be greater than the source voltage which is HS and the Mosfet will be turned ON. Is my understanding correct?

Hi,

It sounds to me like they are missing some words in the description of the operation. The main problem was they quoted' VS' instead of 'VB' for the sum. Let's see if we can rewrite it so the operation is clearer.

"When the lower IGBT is turned off, the capacitor will supply the energy required to drive the upper IGBT into strong conduction. When the upper IGBT starts to turn on, the voltage at VB equals the sum of the DC+ buss voltage and the capacitor voltage, which enables the upper IGBT to turn on all the way. This is also when the voltage at VS approximately equals the voltage of the DC+ buss."

Here is another rewording...
"When the lower IGBT switches off, the capacitor takes over and provides the charge needed to drive the upper IGBT into firm conduction. As the upper device begins to turn on, the node VB rises to the DC‑bus voltage plus the capacitor’s voltage, giving the gate the headroom it needs for a full turn‑on. At the same time, the source node VS is pulled up to roughly the DC‑bus potential."

The basic action here is that of a voltage doubler, if the DC+ bus was equal to Vcc. It can go higher here though because the DC+ bus voltage is usually higher than Vcc. Once the upper IGBT turns on, the approximate voltage of the DC+ bus appears at the source terminal, and since the cap was previously charged, it adds to the DC+ bus voltage.

A little side note is there will always be some short dead time, which is the time when BOTH transistors are off. When the lower one turns off that means the bottom of the cap is open circuited from the transistors for a short time, which means the voltage at the bottom of the cap would probably remain at a low voltage while the top would be roughly at Vcc. If the internal impedance of the VS terminal changes though that could change that, so you'd have to read up on the chip specs to find that out, but it's mainly only during the dead time and the dead time is not always something that is considered in these mini problems.

 

Few questions i have are the HO which is going to High Side MOSFET shall be greater than HS by around ~12V but HB voltage is increased, so i am assuming that HB and HO are connected, but i am not sure if it is direct connection? the data sheet shows logic connections between them.

 

Few questions i have are the HO which is going to High Side MOSFET shall be greater than HS by around ~12V but HB voltage is increased, so i am assuming that HB and HO are connected, but i am not sure if it is direct connection? the data sheet shows logic connections between them.

View attachment 361984

Hi,

Yes according to that little schematic HB (which is VB here) will connect to HO through the drain and source of that upper tiny internal MOSFET transistor. Since HB (VB) is a higher voltage after the cap had been charged, the external upper MOSFET gets driven harder with a higher gate voltage. It's that simple.

 

The above is the sample application circuit from the data sheet, i have attached in previous post. The below is what i have drawn

Can i remove C1 and keep C2 alone? I think C1 and C2 will become parallel and net capacitance becomes C1+C2, i am confused with C1 to retain or remove? Please guide me.

Thank you in advance

 

View attachment 362206

The above is the sample application circuit from the data sheet, i have attached in previous post. The below is what i have drawn
View attachment 362208
Can i remove C1 and keep C2 alone? I think C1 and C2 will become parallel and net capacitance becomes C1+C2, i am confused with C1 to retain or remove? Please guide me.

Thank you in advance

Hi,

Well in the past it was always a recommendation to use one larger value capacitor in parallel with a smaller ceramic. So one electrolytic which can handle larger power supply fluctuations, and one smaller one to handle the higher frequency noise and spikes.
Typical were 1uf and 0.1uf, or 10uf and 0.1uf. The 0.1uf was per chip, the 10uf was for several chips. 4.7uf sounds good along with a 0.1uf or maybe that 470nF would be ok too.
The power supply has to remain stable or else various things go wrong.

 

I have to understand the functioning of the boot strap capacitor, i followed the link Bootstrap it was clear till certain stage then ..
View attachment 361961
The charging part was clear when the lower Mosfet is ON the bootstrap capacitor charges as per VCC(1 - e^{-t/tau}) as it is PWM input, tau = Rboot * Cboot. Now the question is when the top Mosfet is ON there is a statement in the document in the link
View attachment 361963
Is the above statement wrong since the point Vs is directly connected to DC+ it can have voltage of VDC+ only.
I have verified another document TIBootstrap
View attachment 361962of
The point HB should be VDC+ + VCboot (that is DC bus voltage + Voltage of the boot capacitor). There shall be internal connection between HB and HO, then only the HO the gate voltage will be greater than the source voltage which is HS and the Mosfet will be turned ON. Is my understanding correct?

That "VS" is an ordinary typo - should read "VB".

 

Thank you for reply, i have captured few waveforms of VbVs using differential probe with positive on Vb and negative on Vs but not able to understand the waveforms. The blue are the boot capacitor waveforms and yellow phase current.
For the blue waveform the difference is 968mV - 568mV = 400mV, the factor is 20 in the probe so i get 0.4*20 = 8V. I don't know if the waveforms are correct or wrong.

 

Thank you for reply, i have captured few waveforms of VbVs using differential probe with positive on Vb and negative on Vs but not able to understand the waveforms. The blue are the boot capacitor waveforms and yellow phase current.
For the blue waveform the difference is 968mV - 568mV = 400mV, the factor is 20 in the probe so i get 0.4*20 = 8V. I don't know if the waveforms are correct or wrong.

What's the capacitance of your bootstrap capacitor? Usually we'd go for something in the range of 1 .. 10 uF to have sufficient buffering. (If your zero line is correct the bootstrap voltage shows a swing between about 11 and 20 V. Do the 20 V match your supply? IT seems your Rboot is non-existing or may a bit (too) low-ohm.)
The "bumps" during the phase when VS is high (following the steep fall of VB) are not unexpected - current feedthrough through CDG (the "Miller-C" of the MOSFET) when the high-side MOSFET is switching. Add some imperfections of the differential probe . . . and it is as it shows.

 

The bootstrap capacitance value is 4.7uF. I give only VCC = 12V to the Mosfet driver supply i am not sure about 20V.
The internal boot strap resistance is

Typical is 25 Ohm as per data sheet.

 

The bootstrap capacitance value is 4.7uF. I give only VCC = 12V to the Mosfet driver supply i am not sure about 20V.
The internal boot strap resistance is
View attachment 362481
Typical is 25 Ohm as per data sheet.

If the following is your circuit you bootstrap capacitance (unnamed capacitor) is only 1 uF:

(NO - C1 is not the bootstrap capacitor ;-) )
And keeping C1 as well as C2 makes sense as they usually have different impedances. These are meant to suppress EMI effects.
So if the above circuit applies,replace the unnamed 1 uF capacitor by 4.7 uF.

And if my math doesn't fail the operating frequency of your circuit is some 20 kHz. This calls for larger bootstrap capacitances so 4.7 uF might be the lower limit to achieve a stable operation.

 

If the following is your circuit you bootstrap capacitance (unnamed capacitor) is only 1 uF:
View attachment 362582
(NO - C1 is not the bootstrap capacitor ;-) )
And keeping C1 as well as C2 makes sense as they usually have different impedances. These are meant to suppress EMI effects.
So if the above circuit applies,replace the unnamed 1 uF capacitor by 4.7 uF.

And if my math doesn't fail the operating frequency of your circuit is some 20 kHz. This calls for larger bootstrap capacitances so 4.7 uF might be the lower limit to achieve a stable operation.

The challenge i am facing is the motor speed is not reaching max RPM. Yes C1 is not the boot strap capacitor, i replaced boot strap capacitor 1uF with 4.7uF and running at 15KHz frequency, can i increase the boot strap capacitor to 10uF, will it cause any issues? There is motor speed improvement of 200 RPM by changing from 1uF to 4.7uF, but it has not yet reached the max speed of 3.3K rpm at 48V, I could reach only 2.56K RPM. If i increase the modulation index beyond 85% there is no speed improvement. I want to go upto 95% modulation index so that speed can reach the maximum value.

 

The challenge i am facing is the motor speed is not reaching max RPM. Yes C1 is not the boot strap capacitor, i replaced boot strap capacitor 1uF with 4.7uF and running at 15KHz frequency, can i increase the boot strap capacitor to 10uF, will it cause any issues? There is motor speed improvement of 200 RPM by changing from 1uF to 4.7uF, but it has not yet reached the max speed of 3.3K rpm at 48V, I could reach only 2.56K RPM. If i increase the modulation index beyond 85% there is no speed improvement. I want to go upto 95% modulation index so that speed can reach the maximum value.

Try adding a fast Schottky diode, such as a 1N5819, between Vcc and Vb. This should give a faster charge path for the bootstrap capacitor, bypassing the resistance of the internal system.

 

Increasing the bootstrap Cap to 10 uF should not raise any issues - just improving driver/MOSFET performance. (OK - at some point you might need a diode with a higher current rating. But not yet for 10 uF.)

One question: as you mention a "modulation index" (my guess: "duty cycle") beyond 85 %:
What are you trying to operate? A brushed DC motor ? Then the bootstrap capacitor concept is inappropriate and you'd better go for an isolated DC/DC converter to supply the high-side driver. And whether you need a low-side MOSFET or might be better off with a simple freewheeling diode: depends on the current levels. At least the freewheeling diode does not require some dead-time provisions

 

Try adding a fast Schottky diode, such as a 1N5819, between Vcc and Vb. This should give a faster charge path for the bootstrap capacitor, bypassing the resistance of the internal system.

Thank you for replying, the circuit had the diode SS0530 between Vcc and Vb but for some reason i removed it, will mount it back and check for any improvement, i will capture the waveforms and post it.

 

Increasing the bootstrap Cap to 10 uF should not raise any issues - just improving driver/MOSFET performance. (OK - at some point you might need a diode with a higher current rating. But not yet for 10 uF.)
provisions

I will not mount 10uF as of now, but i will mount the diode SS0530.

One question: as you mention a "modulation index" (my guess: "duty cycle") beyond 85 %:
What are you trying to operate? A brushed DC motor ? Then the bootstrap capacitor concept is inappropriate and you'd better go for an isolated DC/DC converter to supply the high-side driver. And whether you need a low-side MOSFET or might be better off with a simple freewheeling diode: depends on the current levels. At least the freewheeling diode does not require some dead-time

I am trying to run the BLDC motor with STM32 motor control code. It is using FOC and SVPWM and modulation index is a configurable parameter for maximum speed the recommendation is going as high as possible, but i could not go beyond 85%, after that i could see the spikes in phase current. Even between 82% to 85% as well the behaviour is not consistent. The speed gets saturated to 2560 RPM.

 

If referring to the STSPIN applikation: that one is not appropriate for bootstrapped high-side drivers. It calls for 3 DC/DC converters (one for each HS MOSFET driver) to achieve 100 % duty cycle with N-channel MOSFETs.
Achieving higher duty cycles usually also needs more sophisticated gate drivers as the turn-on and turn-off times of the MOSFETs are not zero.
"spikes in phase current"? Or more like "spikes in the "leg current""? I'd expect some shoot-through once you violate the minimum dead-time requirement. Not exactly unexpected ;-)

 

Try adding a fast Schottky diode, such as a 1N5819, between Vcc and Vb. This should give a faster charge path for the bootstrap capacitor, bypassing the resistance of the internal system.

Can you please suggest if it can increase the speed? I observed a MOSFET failure after populating the diodes, i am not sure of the exact reason, i have removed the 3 diodes in 3 Mosfet gate drivers at present, may be i have repopulate and test it again.

 

If referring to the STSPIN applikation: that one is not appropriate for bootstrapped high-side drivers. It calls for 3 DC/DC converters (one for each HS MOSFET driver) to achieve 100 % duty cycle with N-channel MOSFETs.
Achieving higher duty cycles usually also needs more sophisticated gate drivers as the turn-on and turn-off times of the MOSFETs are not zero.
"spikes in phase current"? Or more like "spikes in the "leg current""? I'd expect some shoot-through once you violate the minimum dead-time requirement. Not exactly unexpected ;-)

Do you have any recommendation or suggestion to increase the speed by another 200 RPM. The back emf constant of the motor is 12.6 /*!< Volts RMS ph-ph /kRPM */
12.6 - 1000 RPM so for 200 RPM i need to increase the phase voltage by 2.52V? I have increased the boot capacitance by 10uF from 4.7uF but the motor does not spin.