1.
(a) Remove all the internal bubbles in the circuit by applying DeMorgan's theorem so that the circuit consists of only AND gates and OR gates, and INVERTERS. INVERTERS can only be used for the inversion of inputs. Note that there is a 3-input NAND gate shared by both F1 and F3.

(b) Redraw your circuit using the given gates. They consist of four 3-input AND gates, four 2-input AND gates, four 3-input OR gates, and four 2-input OR gates. Draw your circuit in the bottom half of the schematic template.

Minimize the number of gates in your circuit by removing duplicate gates. Minimization by Boolean algebra is not required.

Use G1, G2, G3, G4, G5, and G6 as the outputs of your circuit. If your circuit is correct, the value of G1 should be the same as Fi for i = 1 to 6



I have done part a but I can not draw the circuit using only 4 2-input AND gates. I am using too many gates and I can not figure out how to get it down to 4 gates. Here is the original circuit and my circuit:

I have also attached the logic works file in a zip file.

How can I get it down to the 4 gates that I need? I don't see any duplicate gates.
Please help.
Thank you.

 

If I understand you correctly, you need five 2-input AND gates and you are only allowed to use four such gates, correct? If that's the case, consider that you are allowed to use up to four 3-input AND gates and you are presently only using two.

Does that suggest any options to you?

 

Hmm. I considered this as an alternative but I guess it is the only way. A 3-input AND gate can easily be substituted for a 2-input AND gate, but it's wasteful. However, this must be what needs to be done.

Thank You.

 

It may or may not be the only way, but it satisfies the requirements of the problem. One of the most valuable lessons that an engineer-to-be can learn is that if the answer is good enough, then it is good enough. We (myself most definitely included) tend to like making things as good as they can be, but if we have gotten them good enough to meet the customer's requirements, then we are not justified spending a dime more of their money to make it better.

As for wasteful, getting rid of the bubbles is what's really wasteful. Not counting the four inverters used to generate the complements of the inputs, the original circuit used 18 two-input gate equivalents (72 transistors if implemented in CMOS). The solution (using 5 2-input AND gates) uses 22 two-input gate equivalents (88 transistors in CMOS). The reason is that transistors are inherently inverting and so an AND gate is implemented as a NAND gate followed by an inverter (at least in CMOS). Similarly, an OR gate is implemented as a NOR following by an inverter. As a result, not only does it take up more transistors, but the AND and OR have about twice the propagation delay.

So while this is a reasonable assignment from the standpoint of working with bubble logic, in practice you would use the same techniques to place bubbles on the output of as many gates as you can. Getting good at it is a very valuable skill to have in many jobs.