Hi, I'm working on a textbook question that is giving me some trouble:

A given ALU can perform 16 unique operations. Describe the multiplexer circuit needed to select exactly one of the 16 operations.

I'm not sure what they mean by "operation" other than an operator doing work on a set of operands. Since they don't give the actual operations (ADD, SUBTRACT, etc.) or the bit length, is it reasonable to represent the entire operation as a single bit?

For example, I worked out the truth table and circuit diagram for a 16x1 Multiplexer with a bit length of 1. Obviously an ALU isn't sending 1 bit at a time unless there is sequential timing occurring upstream.. Does this mean a block diagram of a traditional MUX is more appropriate? I like my schematic below because it shows the actual transformation but I fear I haven't adequately answered the question. Thanks for the help!

 

If that's the only information you are given, then it seems like you have to assume that the ALU is designed so that it has difference portions of it that each perform one of the sixteen operations, so you have sixteen subblocks, each of which is producing the output for that subblock's operation, and you need to design a circuit to select one of these subblock outputs to send to the final ALU output. In that case, your approach is along the right lines. Your circuit is choosing one of the bits in the chosen output and providing one of the bits in the final output. If your ALU data path is 32 bits wide, what would you need to do to get all 32 bits to the output of the ALU?

Note that this is not how any rational ALU is set up. In a simple ALU there might be two sections, an arithmetic section and a logic section (and hence the name arithmetic/logic unit) that operate in parallel and then a 2:1 mux to choose between their individual output. Other control inputs would tailor the operation performed by each section.

 

perhaps the 74181 datasheet might help.

 

If that's the only information you are given, then it seems like you have to assume that the ALU is designed so that it has difference portions of it that each perform one of the sixteen operations, so you have sixteen subblocks, each of which is producing the output for that subblock's operation, and you need to design a circuit to select one of these subblock outputs to send to the final ALU output. In that case, your approach is along the right lines. Your circuit is choosing one of the bits in the chosen output and providing one of the bits in the final output. If your ALU data path is 32 bits wide, what would you need to do to get all 32 bits to the output of the ALU?

Note that this is not how any rational ALU is set up. In a simple ALU there might be two sections, an arithmetic section and a logic section (and hence the name arithmetic/logic unit) that operate in parallel and then a 2:1 mux to choose between their individual output. Other control inputs would tailor the operation performed by each section.

A simple approach would be to replicate the circuit 32 times. As long as the order of the bits is maintained, a word of n bits can be constructed at the output.

Aside from that, I think more digital encoding could be done but I'm not sure how. Maybe a circuit consisting of n multiplex stages and n decode stages.

Anyway, here is my 2nd attempt at the problem. The real problem was for 20 operations so bear with me as I'm changing the question a bit.




I think this pretty well answers the question. At least 5 bits is needed to represent 20 inputs. Bits 10100-11111 are not used but could be implemented if 12 more operations are desired.

perhaps the 74181 datasheet might help.

Thanks, I like reading datasheets. Can you suggest a less complex chip? There are 32 operations on the chip you suggested which is a lot to analyze.

 

Hi, I'm working on a textbook question that is giving me some trouble:

A given ALU can perform 16 unique operations. Describe the multiplexer circuit needed to select exactly one of the 16 operations.

I'm not sure what they mean by "operation" other than an operator doing work on a set of operands. Since they don't give the actual operations (ADD, SUBTRACT, etc.) or the bit length, is it reasonable to represent the entire operation as a single bit?

For example, I worked out the truth table and circuit diagram for a 16x1 Multiplexer with a bit length of 1. Obviously an ALU isn't sending 1 bit at a time unless there is sequential timing occurring upstream.. Does this mean a block diagram of a traditional MUX is more appropriate? I like my schematic below because it shows the actual transformation but I fear I haven't adequately answered the question. Thanks for the help!

View attachment 321416

View attachment 321417

Hi,

This sounds like what we had to do back a long time ago before microprocessors became wide spread. We had to design everything. Luckily there were calculator chips around and so we used a calculator chip as the ALU in a lab-built CPU. All we had to do was activate the button (input line) for whatever operation was chosen by the ROM and all that required was a 1 of N decoder. As each instruction came it would be an 8 bit code which would decide on what it was supposed to do, and if it was a math operation it would output part of the code to the decoder. That sounds similar to what you have to do. I suppose you should design the decoder yourself and it looks like you are doing that.

BTW, calculator chips were very slow back then so we had to use a delay to wait for the calculation to finish, especially if it was a trig function or something like that.