AGC Wien Bridge Oscillator not working LTSpice

Thread Starter

Gabriel Perianu

Joined Oct 12, 2019
2
Hello everyone, I am having trouble getting this simulation to work. I am a complete novice at LTSpice, i have to design a Wien bridge oscillator in LTSpice. The gain of the amplifier should be automatically adjusted by using a FET.
I taught I can do that but it seems I was wrong. I have simulated the circuit but the output does not oscillate, see below, I attached a snap of the circuit and the .asc file.

I have tried a couple of other wien bridge circuits of the web, some shown in LTSpice and shown with an output chart but when I add the FET it just doesn't work.
Can any one give me a pointer as to what I am missing how do you make an oscillator oscillate?

Thanks for any advice you can offer.
 

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Alec_t

Joined Sep 17, 2013
10,359
Welcome to AAC!
I suggest you start by getting the oscillator to work without the FET, then try modifying the circuit for FET control.
Your layout is hard to follow as the component arrangement bears little resemblance to a conventional one.
Try re-arranging things, with the positive power supply rail at the top and the negative rail at the bottom.
V1 is incorrectly placed/connected.
Post a link to any schematic you used as a basis for yours.
 

crutschow

Joined Mar 14, 2008
23,334
As Alec stated, get the oscillator to work without the AGC feedback first.

And to help get the oscillations started in LTspice, use the Startup or uic options.

upload_2019-10-12_16-4-14.png
 

Thread Starter

Gabriel Perianu

Joined Oct 12, 2019
2
Hi, thank you for your responses! As a basis for my circ. i used the following (tried to combine them, unsuccessfully tho):AGC osc.PNG wien bridge osc.PNG
 

carloc

Joined Oct 8, 2018
11
You have a diode series connected to a capacitor, D1 and C6.

This never works, meaning that whenever you see that connection it's just plain wrong, no matter the remaining circuit.

There's no discharge path for the capacitor!
 

crutschow

Joined Mar 14, 2008
23,334
There's also a diode and capacitor in series in Figure 12, which can't work.
R2 should be connected from the capacitor to ground, not from the capacitor to the FET gate.
 

Alec_t

Joined Sep 17, 2013
10,359
There's also a diode and capacitor in series in Figure 12, which can't work.
As I read Fig 12, D1 and C1 generate a negative bias voltage for the JFET gate, dependent on the negative-going output of the opamp. But I think C1 needs a parallel resistor to make it a leaky integrator.
 
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