Hello everyone

I have a simple question

I want to design a simple logic circuit that has an output of '0' for 5 clock cycle and '1' for the next five cycle and so on.

I thinking to use a T-type flip-flop with a 5 register connected to feedback to the input.

can anyone suggest me a more simple circuit or other idea.

 

A 4017 decade counter with the top 5 outputs diode-ORed together.

 

A 4017 decade counter with the top 5 outputs diode-ORed together.

Yup, that's good.
Unless it's got to work with TTL.

 

thank you
I think that this is easier to implement than T flip-flop

 

A 4017 decade counter with the top 5 outputs diode-ORed together.

thank you
I think that this is easier to implement than T flip-flop

 

You could also use a CD4068 8-input OR gate, or three CD4075 3-input OR gates connected to five sequential outputs of the CD4017.
The LTspice simulation is show below using three CD4075 gates (in one package).

Note that power and ground pins are not shown.

 

What you need is a divide-by-10 counter.
The 74LS90 has a divide-by-5 and divide-by-2 stage, perfect for what you need.

 

Flash.
I just noticed that the CD4017 has a /Q5_9 output which gives the divide by ten, 50% duty-cycle pulse desired, no added parts needed, as shown below

 

0 - 5 clocks
1 - 5 clocks
What's 0, 1 used for, since they are all output 5 clocks?
It seems like a 50%/50% duty cycle execution procedure, what is the load or next device for 5 clocks?

 

i guess it is for the negative and positive units.

 

i guess it is for the negative and positive units.

I have no idea what that means.
What are the "units"?

 

Here is a variation of the original question, adaptable to many more pulse widths and duty cycles. The leading edges of two of the 4017 outputs either set or reset a simple flipflop, and the leading edge of a third output resets the 4017 to start another cycle. Moving TAP1 adjusts the number of clock cycles the output is high. Moving TAP2 adjusts the number of clock cycles the output is low. Note that TAP2 always must be connected to a higher output than TAP1.

For the variation shown in the drawing, the output is high for 5 clocks and low for 3 clocks. When Y8 goes high it resets the 4017, which immediately pulls Y8 low and drives Y0 high, which sets the flipflop.

U1C and U1D form a simple oscillator, something to do with the two unused gates.

ak

 

I would have to agree that the 7490 variations would be perfect. A look at the data sheet would confirm that depending upon which way the binary FF is strapped, it can be either a standard BCD or a Bi-Quinary counter, Back in the dark ages we had a control unit made by Bunker-Ramo that used the Bi-Quinary numbering system. Of course, that was back in the time before integrated circuits, just lots of transistors, diodes and resistors with a few caps for good measure.