Hi,
I'm new to this forum and haven't read through all the rules yet so apologies if I do something wrong.
I'm designing a data-logger that uses a STM32F4 MCU to interface with: SRAM, Sd card, accelerometer and 2 external ADCs(SPI).
I have done the layout of a few PCBs before but this is my first time laying out + routing a 6 layer PCB with an external SRAM interface, therefore I would really appreciate if I could get some advice/feedback from those who are more qualified.
As you'll notice from the PCB file attached, I have tried to keep trace lengths between MCU and SRAM as short as possible and at similar lengths. However, I think that is not the full story and I might be missing some detail because I read in other forums that the impedance is more important. To that end I did try to use the Saturn PCB tool to try and evaluate the impedance of the tracks but then things got quite complex really fast.
I have also tried to make sure that power traces are as thick, and short, as possible to reduce EMI. Don't know if I achieved the best solution though.
Anyways, cutting a long story short... if people could give me suggestions to improve the PCB or point out mistakes that could cause the device to misbehave, I would really appreciate.
NOTE: PCB was done in eagle 7.6.0 and the size of the PCB cannot be larger that it's current size.
Thanks!

 

what is the difference between the shortest and longest trace between MCU and SRAM? What is the clock speed? I suspect that the overall trace length is so short relative to the speed, that you could omit the meanders alltogether.

Regarding the impedance, I suspect the stackup of the pcb will be such that layers 1 and 3 are close to layer 2, and layers 4 and 6 are close to layer 5, with a significantly bigger distance between 3 and 4. Then, the signals use the power planes 2 and 5 as their reference, so these two should be solid under the traces that go by them.
I don´t see any schematic, but you need to have good decoupling between vcc and gnd in order to use the vcc plane as reference for the traces in layers 4 and 6.

 

Hi kubek,
The distances are all between 25mm-28mm. As for the clock speed...My understanding is that the MCU will be able to access the SRAM at a frequency lower than 84MHz (system clock).
You are right about the stack up, but I should have mentioned it in my first post. The stack up I'm using is:
signal 1
gnd
signal 2
signal 3
vcc
signal 4
This is the stack up which I found to be most commonly used for 6 layers PCB so that is why I have adopted it in my design.
I didn't upload the schematics because I didn't think that it would be needed since this is as PCB related query, however, I can upload a pdf of it if people think it will help them to give me advice.
Regarding the bypass/decoupling...I have ensured that there is at least 1x100nF cap for each VCC pin of all chips, as per respective datasheets.

 

Saturn PCB tells me that the delay on that transmission line is somewhere around 6ps/mm, so a 10mm difference will only skew your signals by 60ps, which is negligible compared to the 10ns clock and guessing 500ps risetime of the signals. I wouldn´t bother with length matching.
So when you get rid of the meanders, you should be able to leave the vcc layer just for vcc, and get better signal integrity altogether.

Wow, you are using 8 different vias, both blind and buried, ist that really necessary? It is gonna cost a lot to manufacture the board. I would try hard to get rid of as many variation as you can, with the meanders gone I guess you should be able to do with much fewer types, maybe even one via 1-6 for the whole board, if you can fit such between the pads of the bga and stay within the manufacturers rules.

 

Hmmmm.... I might have misunderstood you when you asked about the distance between longest and shortest trace. The values I provided earlier are taking the meandering into account.

If I were to route the traces as straight forward as possible then the shortest trace would be in the region of 9mm while the longest would be 28mm. If this difference in trace length is not going to cause any trouble then I could have plenty of space to route all the connections using the same type of via and have the traces further apart from each other.

I was more concerned that by not matching the lengths this would cause data corruption between MCU and SRAM. A few years ago I had a go in routing a 4 layer PCB, also with an SRAM, and because the traces weren't matched in length the interface between MCU and SRAM didn't work properly. However, in that case the traces were ~60mm in length.

I will make those changes but before I start, are there any more suggestions/issues? This way I can try make all the changes in one go (to be more efficient).

btw, thanks for your help so far, it is much appreciated.

 

I have not looked at your PCB layout. But...
You might be able to better equalize the trace lengths by re-assigning the data and address lines to the RAM. As long as all all data lines connect as data and all address lines are connect as addresses then all is well. For example:

MCU RAM

D0 D4
D1 D2
D2 D5
D3 D7
D4 D3
D5 D6
D6 D0
D7 D1

The same can be done for the address lines.

 

Hi RichardO,

Thanks for your post, however, I didn't quite understand what you suggested. Could you explain further what you meant?

thanks

I have not looked at your PCB layout. But...
You might be able to better equalize the trace lengths by re-assigning the data and address lines to the RAM. As long as all all data lines connect as data and all address lines are connect as addresses then all is well. For example:

MCU RAM

D0 D4
D1 D2
D2 D5
D3 D7
D4 D3
D5 D6
D6 D0
D7 D1

The same can be done for the address lines.

 

Hi RichardO,

Thanks for your post, however, I didn't quite understand what you suggested. Could you explain further what you meant?

thanks

When wiring a RAM, you do _not_ need to connect the data and address lines between the MCU and RAM with the names matching. In other words, D0 does not have to connect to D0 and D1 does not have to connect to D1, etc. as long as all of the data lines are uniquely connected as shown in my example.

The same applies to the address lines -- as long as all of the address lines are connected from the MCU to the RAM with all of the lines connected and and none of the address lines connected to more than one address line.

This works because the MCU will always read and write a given data bit to the same location no matter how much the data and address lines are scrambled.

 

When wiring a RAM, you do _not_ need to connect the data and address lines between the MCU and RAM with the names matching. In other words, D0 does not have to connect to D0 and D1 does not have to connect to D1, etc. as long as all of the data lines are uniquely connected as shown in my example.

The same applies to the address lines -- as long as all of the address lines are connected from the MCU to the RAM with all of the lines connected and and none of the address lines connected to more than one address line.

This works because the MCU will always read and write a given data bit to the same location no matter how much the data and address lines are scrambled.

I see...I wasn't aware that this was possible, but thinking about it now it makes some sense. So does this mean that the data, and it's corresponding address, in the SRAM will not be in absolute values.
In other words, if I stored the value 5 at address 10, with the connections randomly assigned, as you suggest, then the value 5 would not be at the physical address 10 but at some other corresponding physical address.
Is that the gist of it?
If that is really true then my routing can get way "cleaner" and not only can I have one type of via, as mentioned in the posts above, but I could also match their lengths.
I'll wait for a confirmation on this as I'm still slightly sceptical if this holds true for all modes/scenarios of the SRAM.
thanks

 

I see...I wasn't aware that this was possible, but thinking about it now it makes some sense. So does this mean that the data, and it's corresponding address, in the SRAM will not be in absolute values.
In other words, if I stored the value 5 at address 10, with the connections randomly assigned, as you suggest, then the value 5 would not be at the physical address 10 but at some other corresponding physical address.
Is that the gist of it?

Correct. And if the data lines are scrambled then the bits would not be stored in their same order in the byte either.

If that is really true then my routing can get way "cleaner" and not only can I have one type of via, as mentioned in the posts above, but I could also match their lengths.

I make no claims that the improvement in routing will be greatly improved. You will have to look at your particular situation and see.
There was a time that the order of address and data lines on CPUs and RAM chips was not logical and so a lot of improvement could be gained. I have not looked lately but I think that things have improved a lot in this respect.

I'll wait for a confirmation on this as I'm still slightly sceptical if this holds true for all modes/scenarios of the SRAM.

As far as I know there is no case where scrambling the connections will create a problem. If you think you see one then let me know.

 

I keep forgetting to mention that this scheme does not work for ROM since the ROM programmer must put the data where the MCU expects it to be.

 

I really appreciate all the inputs so far.
I think I have had more progress in the past few hours than I had in the past few days googleing for information.
Never had I ever come across RichardO's suggestion, and this simplifies routing tremendously, in my view.
Now, in this new scenario... Should I bother with matching the trace lengths?
In my original design I also matched the length of the traces for both SPI communication lines because my idea is to have 2 external PCBs (each with an ADC) which can be connected to this main board.
What should I be looking for regarding the SPI's? Clock frequency is 21MHz and the total distance between the MCU and each ADC will be around 100mm. The distance is smaller than the 1/10th of the wavelength of the clock, so am I right in thinking that length matching is not really necessary? Should I have termination resistors to prevent reflections?
again, thanks for all your suggestions

 

I would worry more about the SPI than the memory lines. 21MHz seems very fast for SPI (can the mcu periphery actually go that high?). Are the two peripherals connected to the same spi line, with the cpu in the middle? That might cause major issues, using a separate periphery for each would be better.

 

I would worry more about the SPI than the memory lines. 21MHz seems very fast for SPI (can the mcu periphery actually go that high?). Are the two peripherals connected to the same spi line, with the cpu in the middle? That might cause major issues, using a separate periphery for each would be better.

This MCU has up to 3 SPIs, one of which can be driven up to 42MHz, therefore, to answer your question...yes, it can go that high. The ADCs are connected to independent SPI peripherals. Otherwise, as you mentioned, I would probably see many issues.
Something else that I forgot to mention in my initial post: I already have this device working using development boards. The purpose of this board design is to fit all the electronics in a compact PCB that fits a specific enclosure.
In the PCB attached, I didn't include any termination resistors at the pins of the MCU because I read that for my case it would be better using termination resistors close to the load. But then again, I also read that you should always have series resistors with signals leaving the PCB through wires.
The main reason I didn't place termination resistors in the SPI lines in this board is because I can't find the space for them.
What would be the suggestion here?

Thanks