Hi,
I'm working my way through "Practical Microprocessors" manual based on 8bit Intel 8085 to try to get a better understanding of how microprocessors work.
There's a section about address decoding that I'm trying to fully understand.


Lines A12 and A13 are high and after the NOT gates, go low. The way I see this is all address lines are low when on the right. So it looks like the NAND gate inputs (10,11,12) are all low, therefore the output of the NAND gate will he high.
The text goes on to say the output of this decoder is true (logic 0) only when this exact address is present on the address bus.
I may be misinterpreting this diagram.
Can anyone please shed some light on this for me?

Thanks,
Gary

 

Welcome to AAC!

Can anyone please shed some light on this for me?

Note the bubbles on the inputs of the NAND. They represent inversions.

A NAND gate will give a LOW output when all of the inputs are HIGH. With bubbles on the inputs, it will give a LOW output when all inputs are LOW.

 

dl is correct. The thing to remember is that many of the logic structures inside a microprocessor or shown in a book are not available as standard TTL or CMOS parts, or are standard parts shown in non-standard ways. An AND gate with inverted inputs and output is an OR gate physically, but an inverted-input-NAND in negative-true logic. The rule that governs how to flip back and forth between positive and negative logic is DeMorgan's Theorem.

ak

 

A NAND with bubbles is actually an OR gate. Repeat after me:

"A LOW AND a LOW is a LOW" that's an OR gate
"A HIGH OR a HIGH is a HIGH" that is also an OR gate

Same thing happens with and AND gate

"A HIGH AND a HIGH is a HIGH" that's an AND gate
"A LOW OR a LOW is a LOW" that is also an AND gate

The exact same gate can be drawn in TWO different ways and have the exact same physical implementation.

 

What @AnalogKid and @Papabravo have said about a NAND with inverted inputs being the same an OR gate is true.

The reason it was drawn as a NAND with inverted inputs instead of an OR gate is that the person who designed the circuit is trying to convey that the operation is AND. If an OR gate had been used, intent is obscured.

 

One is 'cheaper' to build and usually faster.
A CMOS NAND/NOR gate takes one layer and uses 2/3 less transistors of the equivalent AND/OR with two layers.

http://lad.dsc.ufcg.edu.br/epfl/ch03.html#3.4

 

Do not think of the bubbles as NOT gates even though they are.

Think of bubbles to represent ACTIVE-LOW inputs or outputs.

For example, the symbol on the left is a buffer with ACTIVE-LOW output.
The symbol on the right is a buffer with ACTIVE-LOW input.

This is an OR gate with ACTIVE-LOW output.



You may slide "bubbles along the wire" to help you understand the logic better.
When two bubbles collide on the same wire, they cancel and can be removed from the wire.

Gate should be drawn to represent the POSITIVE LOGIC function of the circuit application, not the IC that is used in implementation.
For example, the last gate at F is performing an OR function. The 74LS00 is a quad NAND-gate. The last gate function is an OR function and hence should be drawn as an OR-gate. The drawing on the RIGHT is the preferred way to draw this circuit. Note that the inputs A and B are ACTIVE-LOW inputs and hence are properly labeled as such using A_L and B_L. You can also use /A and /B or A' and B'.

 

Welcome to AAC!
Note the bubbles on the inputs of the NAND. They represent inversions.

A NAND gate will give a LOW output when all of the inputs are HIGH. With bubbles on the inputs, it will give a LOW output when all inputs are LOW.

Thank you all for your very good explanations. I understand that now and in fact if I had've read the appendix in the manual it does explain the bubbles there.

The main question I have now is why is the NAND gate placed where it is? Could it not be moved to any other 3 address lines, therefore outputting the active low signal?
Is the positioning of the NAND gate irrelevant in this implementation?

 

One particular mini-computer used the 74LS266 for address decoding. http://pdf.datasheetcatalog.com/datasheets/50/375549_DS.pdf

 

The main question I have now is why is the NAND gate placed where it is? Could it not be moved to any other 3 address lines, therefore outputting the active low signal?

Not sure what you mean by "any other 3 address lines". The NAND has all 16 address lines as inputs so there are no other address lines.

Is the positioning of the NAND gate irrelevant in this implementation

If the intent is to decode address 3000 hex, it needs to be the way it is.

 

I understand now. It wasn't clear to me in the diagram that the NAND was across all 16 address lines. Thanks.