18F4431 - Assembly - Xtal 4 MHz

2 inputs ADC conversion with Vref+ = Vdd /Vref- = ground - one shot mode (every 3 seconds) with simultaneous sampling - Tacq = 2 TAD as per datasheet.

10-bit values read sequentially from the ADRES buffer.

For testing, the inputs come from two resistive dividers (total R <5K ea). Noise is around 5 mV pk to pk in both.

I implemented oversampling (12-bits) to get 1,2 mV resolution. Maths for it and for scaling seem flawless and basically I am getting on the display, steady values with 1 to 3 mV difference with the inputs.

What puzzles me is that at a certain input values, I can start getting periods that could last up to several seconds where one of the channels jumps back and forth from the "correct" value to one that is, most of the time, some 7 to 9 mV above and fixed. Never anything in between. That variation, has not a timing pattern that I could say.

Examples:

Measured at the input: 2456 mV
Result on display: 2458 mV
Value occasionally offset to: 2465 mV

Measured at the input: 1639 mV
Result on display: 1641 mV
Value occasionally offset to: 1650 mV

I ruled out this as specific of a particular AN in the micro by swapping inputs / dividers and appears as occurring for some values. I swapped micros as well.

I am puzzled by the fixed offset that does not change.

My question: could this be an artifact of the oversampling? I do not see why but I ask simply because I do not know whom to blame.

What anyone would suggest to look at? Gracias.

 

Sometimes a fixed offset can be traced to not enough acquisition time i.e. the delay after changing channels to allow the holding capacitor to fully charge to the input voltage. Any analog source resistance can cause the charging time to be longer than expected. Also, be sure you have the conversion clock set as fast as possible for your setup.
You are using Vdd as a reference. Does whatever you are measuring track any Vdd drift? If not, you could be experiencing an effective Vref drift.
Is Vdd well decoupled with high and low value caps on all Vdd pins?
Do you have a solid ground. The low analog ground (and Vref-) should go back via separate wires to the ground reference point of the analog source. That way, it doesn't share ground current with the noisy digital stuff and is not subject to ground offsets due to current in the supply wires.
You might try an external Vref to see how that goes.
Those are the easy things to check.

Good luck.

 

Hola John,

Sometimes a fixed offset can be traced to not enough acquisition time i.e. the delay after changing channels to allow the holding capacitor to fully charge to the input voltage. Any analog source resistance can cause the charging time to be longer than expected. Also, be sure you have the conversion clock set as fast as possible for your setup.

I tried 4 TAD for TACQ and things went maybe even worst.

Those 2 channels are always selected because basically all what I do is reading the inputs, process, scaling and display.

The clock gives no options as per the datasheet.

You are using Vdd as a reference. Does whatever you are measuring track any Vdd drift? If not, you could be experiencing an effective Vref drift.
Is Vdd well decoupled with high and low value caps on all Vdd pins?
Do you have a solid ground. The low analog ground (and Vref-) should go back via separate wires to the ground reference point of the analog source. That way, it doesn't share ground current with the noisy digital stuff and is not subject to ground offsets due to current in the supply wires.
You might try an external Vref to see how that goes.
Those are the easy things to check.

OK I will start rechecking, and probably improving, all the above.

Gracias.

 

The clock gives no options as per the datasheet.

Did you look at ADCS<2:0> in ADCON2 and Table 21-2? That sets TAD then you see if that's enough real time to satisfy TACQT .

 

Hola John,

I have set TAD =2 TOSC =500nsec and
TACQ =4TAD =2usec

Additionally, noise is now higher, around 15 mV pk to pk what seems to ensure effective oversampling (no more fixed offset).

All in all, wobbling in the display is 1 mV for both channels.

What I concluded as well is that using Vdd as Vref+ is a recipe for disaster. Tomorrow I will be reworking the whole thing and set a proper Vref ad hoc.

It is good to see something that decides to finally work OK.

Gracias again for replying.