The MOSFET is turning off exactly when you tell it to and with great speed, so according to post #1 there is no problem there. To make the output voltage look better, add a resistor from the opamp output pin to the -5 V. The value can be what is required to sink 10% of the opamp's output current, leaving 90% to charge up the FET.

ak

 

I have modified schematic a bit. Please see picture Opamp_FET. Now opamp is more stable. But there a things that i cannot find explanation, maybe you could help :

1) The actual Voltage on sense resistor is about 25 smaller that set voltage.. Where is it wasted? Is it on MOSFET Rds? (see picture "smaller amplitude")

2) There is a delay between signal generator voltage rising edge (set current) and actual current wavevorm rising edge.The higher the current the smaller the delay. With very small current the delay gets bigger.. Why? (se pictures Delay1, Delay2)

3) Please see picture "MOSFET turns off". Mosfet current falls to zero at point when signal generator output falls down. It's good. But gate voltage at this point is still higher than required to keep mosfet turned on. Why does it turn off?

Some ideas.
Fast op amp capable of moderate current.
Use a FET with the lowest gate charge that will handle the power you want.
Minimize the gate resistor and rolloff cap.
Here is an example:

 

Some ideas.
Fast op amp capable of moderate current.
Use a FET with the lowest gate charge that will handle the power you want.
Minimize the gate resistor and rolloff cap.
Here is an example:
View attachment 126357

Hello Ronv, thank you very much for ideas! I will try them and post results here.

About the opamp:LT1259 is current feedback opamp. I used voltage feedback amplifiers previously. Is current feedback somehow better in my application or you just selected it by accident? Also, LT1259 output current is 60mA. Is it sufficient to charge gate capacitance in 100ns? Maybe you could recommend another op-amp, because at farnell this opamp is only in thru-hole package.. (maybe there are some parameters that tell about ability to drive capacitive loads or specific type of opamps that can handle Capacitive loads well, because when i searched for opamps it was pretty had to find, some datasheets wont even tell any word about capacitance and stability)

The FET: BSC024NE2LSA seems pretty good, but It has 23nC gate capacitance. I have previously selected PSMN017-30PL. Its gate capacitance is 5.1. Maybe it is better?

 

Hello Ronv, thank you very much for ideas! I will try them and post results here.

About the opamp:LT1259 is current feedback opamp. I used voltage feedback amplifiers previously. Is current feedback somehow better in my application or you just selected it by accident? Also, LT1259 output current is 60mA. Is it sufficient to charge gate capacitance in 100ns? Maybe you could recommend another op-amp, because at farnell this opamp is only in thru-hole package.. (maybe there are some parameters that tell about ability to drive capacitive loads or specific type of opamps that can handle Capacitive loads well, because when i searched for opamps it was pretty had to find, some datasheets wont even tell any word about capacitance and stability)

The FET: BSC024NE2LSA seems pretty good, but It has 23nC gate capacitance. I have previously selected PSMN017-30PL. Its gate capacitance is 5.1. Maybe it is better?

Your FET would be better. When I run the simulation with that gate charge I can eliminate the gate resistor and use only 2.2 pf (probably no) roll off cap. The op amp current I see with it is about 20Ma from the op amp.
I just chose a fairly fast op amp.

 

Hello, i tried ronv suggested componet values,except i didn't mount R4. Also opamp and FET is also different than suggested. I attach my tests in PDF. Could you suggest how to make circuit work in lower frequencies?

 

Hello, i tried ronv suggested componet values,except i didn't mount R4. Also opamp and FET is also different than suggested. I attach my tests in PDF. Could you suggest how to make circuit work in lower frequencies?

Remember the funny gate wave form?
As the off time increases the gate returns closer to ground, so the next pulse needs to rise from a lower voltage. Since the rise time is not super fast it takes longer.
On thing you might be able to do to improve it would be to use a transistor instead of a FET. then the difference between long and short would only be .6 volts instead of 2 or 3 volts.
Are you sure your probe is properly compensated?

 

Hello, i tried ronv suggested componet values,except i didn't mount R4. Also opamp and FET is also different than suggested. I attach my tests in PDF. Could you suggest how to make circuit work in lower frequencies?

Here is an improvement we can do to improve the gate signal.

 

Hi, i changed the FET to logic level PSMN017-30PL. The vawevorm got better, but still with ringing. With your last suggestion i don't see current waveform at all.. Input is 200mV pulse..

 

You asked about probe compensation - i'm not sure. The probes are Agilent N2863A 10:1 , 10M || 15pF

 

Update: i changed some component values, and the waveform look pretty nice.Here is the schematic




What should i do to eliminate that noise at the beginning and also that delay?
Maybe i should try to use dedicated gate driver between opamp and MOSFET?

 

Update: i changed some component values, and the waveform look pretty nice.Here is the schematic
View attachment 126504

View attachment 126505

What should i do to eliminate that noise at the beginning and also that delay?
Maybe i should try to use dedicated gate driver between opamp and MOSFET?

The logic level fet is a good idea. The delay is caused by the rise time of the op amp. It is aggravated because you have to slow it down with the cap to maintain stability.

If you look at the simulation the output of the op amp has to rise to the threshold voltage of the FET. That's why a NPN transistor would be better. The voltage would only have to rise to .7 volts or so.
You can improve your current circuit by making the gate resistor smaller. This will let you make the cap across the op amp smaller and maintain stability. And as before the lower the gate charge the better. The noise is probably from the layout or component placement. It's a high frequency op amp so it would like a ground plane and good decoupling on the power supplies. Very short leads etc.

 

Update: i changed some component values, and the waveform look pretty nice.Here is the schematic
View attachment 126504

View attachment 126505

What should i do to eliminate that noise at the beginning and also that delay?
Maybe i should try to use dedicated gate driver between opamp and MOSFET?

I forgot... Usually when you measure transient response of a power supply it is not measures from zero to some value, but from some percentage of maximum load to some value. If measured from say .2 amps to 2 amps you would be in good shape.