A self-latching "pulse stretcher" LVPECL comparator, AKA: "ECL ain't trivial"

Thread Starter


Joined Apr 20, 2012
Hi everyone!

I attempting to implement an ECL comparator, but unfortunately my lack of experience with ECL logic is getting the best of me. My goal is simple: Make an ultrafast version of this pulse stretcher, using an ADCMP553 from Analog Devices. The pulses I wish to detect are extremely narrow (~1ns), and thus I must use a fast comparator, and therefore ECL is naturally involved.

In a perfect world, I could simply implement it as I would a regular comparator. The main problem, as far as I see, is the combination of the large input currents for the complementary latches (150 uA each, I think. The datasheet was a bit confusing for these values.), and the fact that the ECL comparator outputs can only source current, not sink it. After some thinking, I have come up with a possible solution but I wish to hear the opinion from someone who might know this better than me.


In this scenario, the comparator (only the complementary output is modeled) will trigger on an input signal, and the complementary output will go from high to low at some time t. The capacitor then discharges through the 50 ohm resistor until reaching the logic low level of ~1,5V with an RC time constant of 0,5ns. This in turn drags the complementary latch input low too, latching the comparator. The latch input will source 150uA, charging the capacitor and eventually it will "see" logic high. Another way of thinking of it is that the latch input is floating at DC, but connected to the comparator complementary output at AC via the decoupling capacitor. The datasheet states that the latch inputs have internal pullup resistors, and thus will default to their unlatched state if left floating. I therefore imagine that when the capacitor has been charged enough for the latch input to see logic high (or float, however you wish to look at it), the comparator will become unlatched again. The comparator complementary output will then go from logic low to logic high, charging the capacitor to logic high. This raises the latch side of the capacitor well above logic high. To prevent this excessive voltage on the latch input, a zener diode is added to quickly bring the voltage down to logic high + zener voltage drop.
The scheme will be similar for the normal, not complementary, latch input. They must both be driven, according to the data sheet. Except here, the capacitor will be connected to the non-complementary output, the latch input will sink, not source, and the Zener diode will be connected to ECL low level.

So this is my idea. However, I am not sure if I have the correct understanding of how the latch inputs work to say for sure that it will work. For example, will they both truly sink and source 150uA? I could not understand the datasheet on this. What happens in the boundary when the capacitors are being charged/discharged by the latch inputs and the logic level they see is somewhere between high and low? I cannot have weird effects like the comparator switching between latched and unlatched state.

In addition, does the latch inputs simply turn latching on or off for each of the comparator outputs? In this case I will only need to drive a single latch input, since I anyways only will keep the signal from one of the comparator outputs. The latch related to the other output could then be left floating to do as it pleases.

Thanks for reading this long post!
Regards, Pinks