Hello everyone, I'm currently working on a digital circuit design. I'm having trouble figuring out a concept for assembling 8x 1 to 8 demultiplexers in a way that consumes minimal digital outputs. I have an NI-DAQ card with 16 digital IO, and I want to use as few digital outputs from my DAQ card as possible—ideally just around 8 bits to control the demultiplexers. How can I solve this problem? Has anyone built something similar and has a sample circuit ready for me?

 

Hello everyone, I'm currently working on a digital circuit design. I'm having trouble figuring out a concept for assembling 8x 1 to 8 demultiplexers in a way that consumes minimal digital outputs. I have an NI-DAQ card with 16 digital IO, and I want to use as few digital outputs from my DAQ card as possible—ideally just around 8 bits to control the demultiplexers. How can I solve this problem? Has anyone built something similar and has a sample circuit ready for me?

So, a 74HC138 is an example of a demultiplexer with 8 outputs. It has three select inputs and three enable inputs. For 8 devices that amounts to 48 inputs. I fail to see a strategy that requires less than three NI-DAQ cards to solve in the general case. You might have a chance to reduce that number if some of the inputs can be common or tied to fixed values. You have neglected to reveal any useful information for optimizing this situation.

 

Or you could drive the card select bits from an I2C port expander. A PCF8574 will give you 8 port pins, and the PCF8575 or MCP23017 will give 16, all on a shared pair of pins from your micro.
https://www.ti.com/product/PCF8574
https://www.ti.com/product/PCF8575
https://ww1.microchip.com/downloads/en/devicedoc/20001952c.pdf

 

It is actually only 3 bits per demultiplexer if all outputs are enabled always. Which is 24 bits.

Are there other restrictions on which outputs can be active at the same time? If so, it might be possible to compress the info into 16 bits, but that seems unlikely without lots of extra logic.

A general solution is to send the data in two 12-bit chunks, using the other bits to latch them into double buffered latches.

This solution assumes 12-bit buffered latches that have one input to latch data to the buffer on trailing edge and another to transfer buffered data to the outputs.

Put the first 12 bits on the bus bits 0-11 plus but 12 high. Bit 12 is used to latch the first latch. Then change bit 12 to low to latch it. Next put the second 12-bits on 0-11 and bit 13 high as the latch for the second set of 12. Then clock bit 14 up and down to transfer all latched data on both to the outputs, which drive the inputs of the multiplexers.

 

Can you post some info on your card as that will help a lot.

 

I think you need to use at least one of the enables as the data to be demultiplexed. Sadly, the TS did not bother to describe his intentions in much if any detail.

 

I would have given you more information if I had it. Unfortunately, that's all I have. To control the outputs of a 3-to-8 module, I need 3 bits. If I connect several modules, this leads to a considerable consumption of digital channels.

If I have 4 boxes with a 3-to-8, each box will receive 3 lines, making a total of 12.
Alternatively, all boxes could be connected in parallel, which would mean that all 4 boxes would show the same signal. In a parallel setup, all lines would have the same state.

Therefore, I need additional wire to select the individual boxes - a kind of "chip selector" or "box selector".
With such a selector, I could indicate which box is active, for example by selecting 'Box A' or 'Box B', and so on." However, I would like to control not just 4, but 8 boxes to ensure expandability. I would need 8 lines for this. A circuit would have to be developed that can control 8 boxes with 3 lines. In any case, there must be reserve channels left on my DAQ 6212 measuring card.

I have a deadline meeting tomorrow where I have to present a concept, preferably a block diagram, and I really have no idea.
Maybe the explanation is a bit too vague. I apologize for my poor English. English is not my mother tongue.
tank for your suggestions.

 

Hi Man,
Using HCT138 mux, is this method close to what you had in mind.
A two Part address of 3Bits + 3 Bits = 6 Bits in Total

E

 

I would have given you more information if I had it. Unfortunately, that's all I have. To control the outputs of a 3-to-8 module, I need 3 bits. If I connect several modules, this leads to a considerable consumption of digital channels.

If I have 4 boxes with a 3-to-8, each box will receive 3 lines, making a total of 12.
Alternatively, all boxes could be connected in parallel, which would mean that all 4 boxes would show the same signal. In a parallel setup, all lines would have the same state.

Therefore, I need additional wire to select the individual boxes - a kind of "chip selector" or "box selector".
With such a selector, I could indicate which box is active, for example by selecting 'Box A' or 'Box B', and so on." However, I would like to control not just 4, but 8 boxes to ensure expandability. I would need 8 lines for this. A circuit would have to be developed that can control 8 boxes with 3 lines. In any case, there must be reserve channels left on my DAQ 6212 measuring card.

I have a deadline meeting tomorrow where I have to present a concept, preferably a block diagram, and I really have no idea.
Maybe the explanation is a bit too vague. I apologize for my poor English. English is not my mother tongue.
tank for your suggestions.

I sympathize with the TS's situation of being in a "sink-or-swim" position. It is most definitely not your fault, rather it is the fault of your "management" in giving you a task for which you are unprepared. It is their failure for not having people with the experience to handle problems in unfamiliar territory. Keep your head down and do your best.

 

It is actually only 3 bits per demultiplexer if all outputs are enabled always. Which is 24 bits.

If you use a 9th 8:1 demux to select the other 8 demuxes, the total bit count is 6 bits. This makes sense, since eight 8:1 demuxes is 64 outputs which is 2^6, so the absolute minimum number of parallel driver bits is six.

As you said, that assumes no additional output gating/strobing etc.

Note that the 74xx138 output are inverted - the selected output goes low, and all other non-selected outputs are high.

I see now that eric posted this in #8.

ak

 

Thanks for your support. I have it on a sheet of paper. it looks a bit messy, but I hope you can understand my sketch. A two Part address of 3Bits + 3 Bits (CS) = 6 Bits in Total

 

Hi Man,
That looks inline with what I have proposed.
E

 

Hi Man,
That looks inline with what I have proposed.
E

Yes, that's why I thanked you all for your support.

 

You should add output bubbles so it is clear that the selected output goes low rather than high. Other than that, looks good.

ak

 

Shift registers are an easy alternative to combinational logic circuits. Provided the timing is correct, you can shift as many bits as you want with a single clock input.



https://docs.arduino.cc/tutorials/communication/guide-to-shift-out

 

Shift registers are an easy alternative to combinational logic circuits. Provided the timing is correct, you can shift as many bits as you want with a single clock input.

Yes.
A serial-to-parallel SR would allow control of an arbitrary number of Mux address bits as long as you do not necessarily need maximum mux sequence speed.
It could be done with three micro outputs--clock, serial, data, and group mux enable.
The group enable signal blocks the mux outputs when the SR is shifting to a new mux address.
The SR parallel output would be the mux address plus the specific mux enable bit.
Thus controlling eight 8-bit muxes would require 3 address bits plus 8 enable bits, so two 8-bit parallel-out SR's would work.
Each mux channel output selection would be an 11-bit serial shift into the SR.

Alternately if you used a 3-bit to 8 output enable chip, then that would only require 6 control bits, using one 8-bit SR,

 

OR, stick with the shift register approach and eliminate the muxes.

The CD4094 is an 8-bit shift register that has a latch between the shifters and the outputs. Shift out a 64 bit pattern that is sixty-three "0"s and one "1", then toggle a strobe line that goes to all eight devices.

ak

 

They have really cool suggestions, but I'm still very new to digital circuitry, so it's difficult for me to realize such circuits quickly in practice. I presented my concept to them, they liked it, but they want the addressing to be in the module and not an extra module, i.e. this 1:8 before the DAQ should be replaced by e.g. a 74LS85 and this should be in the module so that the bits for addressing go from the DAQ directly into the module without an extra component in between. Each module should be connected independently to the device so that we do not need any additional modules in front of it. This creates a direct connection between the measuring device and the individual modules, without another device in between. In addition, you then have two bus systems: one for addressing and one for data transmission. Each module we have should have an adjustable address coding. I wish I could understand such tasks quickly

 

I don't know how to realize such a circuit.

 

I don't know how to realize such a circuit.

Not to worry. We are here to help you.

You have four 3-to-8 demultiplexers. Hence you have 32 output control signals.
If you use a serial shift register approach, you would need 3 output lines, DATA, CLOCK, LATCH.
This design is expandable to any number of output signals, plus you have the ability to enable one or multiple units at the same time.