8051 sbit

Thread Starter

Dritech

Joined Sep 21, 2011
901
Hi all,

I know that there are quite a few sites explaining the sbit function, but with reference to the code below (which is using a timer) is the sbit setting bit 0 of port 2 as output? If no, which instruction is setting the port as output?
Also, is "out = ~out;" inverting the state of the output? (i.e. if the output is high, change to low and vice versa).
And the last question, in instruction "while(TF0 == 0); ", will the program stay looping in this same line until TF0 not equal 0 ?

Any help would be appreciated.

Code:
sbit out = P2^0;    

void main(void)
{
   TMOD = 0x0;      
   TH0  = 0xE1;        
   TL0  =  0XFF;  
   TF0  = 0  ;      
   TR0  = 1  ;      
  
   while(1)       
   {
     out = ~out;   
     while(TF0 == 0); 
     TR0 = 0;
     TH0 =  0xE1;
     TL0 = 0xFF ;
     TF0 = 0;
     TR0 = 1;
   }
  
   }
 

Papabravo

Joined Feb 24, 2006
21,159
The sbit statement doesn't do anything. It is a definition, like #define. It says that whenever you see the symbol "out", it means use the address of Port 2 bit 0.

So "out = ~out" is a read modify write instruction to read the value of P2.0, complement it, and write it back to P2.0
 

Thread Starter

Dritech

Joined Sep 21, 2011
901
Thanks for the reply @Papabravo .

I didn't quite understand the role of "out = ~out".
Is the pulse generated by the timer being outputted at P2.0?
If so, which instruction is setting P2.0 as output?

Thanks.
 

Papabravo

Joined Feb 24, 2006
21,159
The statement:
out = ~out ;
does three things. If you could see the assembly language output from the compiler you would see it:
  1. Read the present value of P2.0
  2. Complement that value. ie 1 ⇒ 0, or 0 ⇒ 1
  3. Write the new value back to P2.0
I don't remember if the 8051 can do this operation in a single instruction or not. I'll find out if you really want to know the answer.

EDIT: The instruction is CPL bit, where bit is the address of the bit to be complemented. If bit is the address of P2.0 (0xA0), then it reads the value of the P2.0 data latch, complements it, and wites it back. Easy Peasy.
 
Last edited:

Thread Starter

Dritech

Joined Sep 21, 2011
901
So since the statement "out = ~out ;" is used, there is no need to set the pin as output of start of program execution right?
 

Papabravo

Joined Feb 24, 2006
21,159
So since the statement "out = ~out ;" is used, there is no need to set the pin as output of start of program execution right?
The 8051 does not really have bidirectional ports like some other processors. It has what are called "quasi-bi-directional ports. They work as follows:
  1. If you write a '0' to the port data register it turns on a hard pulldown transistor capable of sinking several milliamps.
  2. If you write a '1' to the port data register it turns on a weak pullup transistor capable of sourcing a couple of hundred microamps or less.
The weak pullup can be taken low by an external source without damaging anything. So all pins are output pins, but an input is a pin with a '1' in it's output data latch.

A crafty compromise for 1978 when the part first came out.
 

cmartinez

Joined Jan 17, 2007
8,220
The 8051 does not really have bidirectional ports like some other processors. It has what are called "quasi-bi-directional ports. They work as follows:
  1. If you write a '0' to the port data register it turns on a hard pulldown transistor capable of sinking several milliamps.
  2. If you write a '1' to the port data register it turns on a weak pullup transistor capable of sourcing a couple of hundred microamps or less.
The weak pullup can be taken low by an external source without damaging anything. So all pins are output pins, but an input is a pin with a '1' in it's output data latch.

A crafty compromise for 1978 when the part first came out.
That would depend on the 8051 particular model being used. The "classic" 8051 works with quasi-bidirectional i/o's as you say. But more recent models (such as Atmel's AT89LP4052) allow you to configure the port's pins as hi-z inputs, push-pull outputs, open collector outputs, or quasi-bi, depending on how you configure a couple of new registers.
 

Papabravo

Joined Feb 24, 2006
21,159
That's a good point. I was of course referring to the classic architecture introduced by Intel in 1978 and copied by all of the second source providers. After Intel abandoned the family in the 1990's, the second source providers were free to innovate and expand their offerings to capture new markets. It appears that they have done so.
 

cmartinez

Joined Jan 17, 2007
8,220
That's a good point. I was of course referring to the classic architecture introduced by Intel in 1978 and copied by all of the second source providers. After Intel abandoned the family in the 1990's, the second source providers were free to innovate and expand their offerings to capture new markets. It appears that they have done so.
They didn't innovate on just that, one of the most important changes was the clock cycles taken per instruction, it used to be multiples of 12, with the most basic NOP instruction taking 12 clock cycles, for instance. Now they work on multiples of one clock cycle, effectively making them much faster. The NOP instruction is now a single clock cycle.
 
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