Hi, I have a question about 8051 microcontroller,
when the content of the D-Latchs a=is the same as pins, and when they are different?

 

The standard 8051 has what are known as quasi-bi-directional port pins. Here is how that works. When you write a logic to the data (D-latch) port it enables a "weak" pullup fabricated on the chip with a MOS transistor. This pullup is so "waek" that an external driving source can easily force it to a logic "low". This means that a port pin with a '1' in the D-latch can also serve as an input. This description applies to ports 1, 2, and 3 assuming they are not being used for auxiliary functions.

Port 0 has open-drain outputs that require an external pullup resistor. I do not believe there is an internal "weak" pullup on Port 0 pins, but it has been a long time since I had to deal with this problem and my memory might be a bit fuzzy.

This approach eliminated the need for a DDR (Data Direction Register) that was popular on Motorola and MOS Technology processors of that era. In that era, silicon area was more precious than bitcoin still is today.

See the following image

 

Hey, Thank you for the explanation,
I still didn't really understand how that can create a difference for pins and D-latchs values, could you please clarify more?

 

Hey, Thank you for the explanation,
I still didn't really understand how that can create a difference for pins and D-latchs values, could you please clarify more?

If you refer to the diagram in post #2, the internal "weak" pullup is represented by a graphic that looks like a European resistor. In the silicon it is fabricated as a MOS transistor with an impedance of about 40K Ohms. When a '1' is written to the latch, the Q*(Q-bar) output will be a zero, and the transistor labeled "N" will be off, disconnecting the pin from GROUND. This lets the "weak" pullup bring the pin to a 'high' state. Remember, this is a "weak" pullup. Any strong current sinking device can pull it 'low'. In this condition the pin and the latch have DIFFERENT values.

 

If you refer to the diagram in post #2, the internal "weak" pullup is represented by a graphic that looks like a European resistor. In the silicon it is fabricated as a MOS transistor with an impedance of about 40K Ohms. When a '1' is written to the latch, the Q*(Q-bar) output will be a zero, and the transistor labeled "N" will be off, disconnecting the pin from GROUND. This lets the "weak" pullup bring the pin to a 'high' state. Remember, this is a "weak" pullup. Any strong current sinking device can pull it 'low'. In this condition the pin and the latch have DIFFERENT values.

I got you, thank you so much for your amazing explanation, good luck !