# 60 second timer issue

#### Jacob Riggs

Joined Mar 18, 2015
4
Hi, I am trying to create a 60 second timer which counts to 60 and then resets to 00 and continues to count up. The design must be done with a 74LS163 for the ones digit and an asynchronous counter designed with J/K flip-flops for the tens digit. Both are connected to 74LS48 BCD to Seven Segment decoders.

Currently, I am capturing the 6 from the tens counter and the 1 from the ones counter and wiring this to both the clears of the J/K flip-flops and the clear of the 74LS163. This causes it to reset from 60 to 01. If I instead only capture the 6 from the tens counter, it will reset at 59 to 00.

How can I reset at 60 without displaying a 01 immediately after it resets?

#### JoeJester

Joined Apr 26, 2005
4,390

#### Papabravo

Joined Feb 24, 2006
21,022
Why do you want a timer with 61 states?
How does clearing the '163 cause it to display a 1?
There's a strange disturbance in the farce, Luke.

#### LDC3

Joined Apr 27, 2013
924
If it's a continuous counter, why would you display 60, 00, 01? That would take 61 seconds to complete one rollover.
You would want it to display either 59, 60, 01 ... or 59, 00, 01 ...

#### Jacob Riggs

Joined Mar 18, 2015
4
I can't seem to upload the file from this computer (or open it to screenshot, this computer does not have the software), but will be able to tomorrow morning. As for your questions, this is a homework assignment, which is why it is in the homework help thread. I do not control the criteria of the assignment.

#### Papabravo

Joined Feb 24, 2006
21,022
A sixty second timer that has sixty one states is a foolish foolish thing and you need to say so.

I'll bet you'll just go ahead and follow orders like a good little trooper? The world needs more of that fer sure!

#### MrChips

Joined Oct 2, 2009
30,503
You really need a counter that goes 00 - 01 . . . 58 - 59 - 00 - 01 . . .

Use two 74LS160.

#### Bill B

Joined Nov 29, 2009
61
Are you sure you understand the assignment? Keep in mind, 0 to 59 is 60 states. In other words, if you increment 60 times starting at 0, you will end up at 59. I would ask for a clarification. I agree with the others, a counter with 61 states makes no sense at all.

Last edited:

#### Alec_t

Joined Sep 17, 2013
14,227
Do you want the display to show 0-59 or 1-60?

#### Jacob Riggs

Joined Mar 18, 2015
4
Here are the criteria and the information I was given in order to create the circuit. These are not subject to change. If I tell my teacher that this is a "foolish foolish thing", he will likely tell me to follow the lab as it is written.

Design a digital Sixty Second Timer that counts from 00 to 60. This design has two control inputs and two output displays. The two inputs are Clock and Reset. The Clock signal is a 1 Hz square wave that controls the count rate. The Reset signal, when it is a logic zero, resets and holds the count at zero. When the Reset signal is a logic one, counting is enabled. When the count reaches sixty seconds, the counting resets to zero.

· The two output displays are common cathode seven-segment.

· Each display will use a 74LS48 BCD-To-Seven-Segment display driver in Design Mode. (DEC_BCD_7 in PLD Mode)

· The ones-unit display (0-9) is controlled by a synchronous counter designed with a 74LS163 MSI counter IC. (CNTR_4BIN_S in PLD Mode)

· The tens-unit display (0-6) is controlled by an asynchronous counter designed with SSI logic gates (J/K).

· Any additional logic may be used as needed to support the counter designs.

I have also included a picture of my current schematic. Thanks for any help!

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#### Jacob Riggs

Joined Mar 18, 2015
4
Ok, our teacher just walked into the room and said that he will now accept 00-59. GG

#### WBahn

Joined Mar 31, 2012
29,878
My guess is that his thinking was that the timer would take one second to go from 59 to 60 and then immediately reset from 60 to 00 and then take the remainder of that second to go from 00 to 01. The user would likely never see the 60 displayed because it would be so brief.

I'm more disappointed in them requiring you to do the tens digit as an asynchronous counter, particularly if they aren't requiring you to do the design verification that asynchronous logic requires in order to do it right.