Hello!
I am designing a 60 degree phase shift circuit, and your idea helps me a lot !
But I don't know can the U1C and U1D be replaced by 2 Nand gate (not schmitt 2 Nand gate)?
And will there be some Race and hazard in the circuit?
Thanks !

My guess is that he used Schmidt trigger input NAND gates only because he needed that for the oscillator circuit that UA1 is a part of and he just used the other gates for the reset logic.

Any time you design asynchronous logic, you have to carefully analyze it to ensure that it can't produce critical glitches or timing hazards, so it's a very good thing that you are thinking about these things (few people do).

In this case, things should work out okay. All three FFs are clocked with the same signal, so the outputs are going to change at about the same time (but in unknown order) shortly after the clock rising edge. The output of the first and third are being used to reset the second, so there's no concern about race conditions because it doesn't matter which signal gets to the NAND gates first. It also doesn't matter whether there are glitches when the reset is asserted since it doesn't matter if it gets asserted one time or a dozen times.

What needs to be looked at more critically is whether there are any static-0 hazards for the reset signal for the second FF. In other words, is it possible, given that the first FF output might change before the third or it might be the other way around, for there to momentarily be a HI at both inputs of the NAND gate during a state transition that should NOT reset the second FF.

To do that, you need to walk though every possible state change and see what happens under each possibility. In this case, you discover that the reset logic appears to serve no purpose.

But that's an illusion.

This is a six-state Johnson counter, that is intended to cycle through the sequence:

000 -> 100 -> 110 -> 111 -> 011 -> 001 (and repeat)

(These are the values of the Q outputs, notice that his QC is coming from the Qbar of the middle FF).

When the system is running through this sequence, the only time that both inputs to the reset logic are HI are when the first and third FFs are LO (since it's the Qbar outputs from each going to the reset logic). This will force the middle FF to reset to LO, which it already is.

So what does it do?

Well, there are eight possible states and the Johnson counter doesn't use two of them, namely 010 and 101.

What if the circuit powers up in one of those two states?

This would result in a two-stage counter that would go

010 -> 101 (and repeat)

So in either of these states, it will quickly get to 010, which will trigger the reset logic, forcing it to go to 000 and then back into the desired sequence.

The same would hold if a cosmic ray or some other glitch upset one of the FFs and put the circuit into either of these two states.

Do note that, in his simulation, he leave unused inputs floating. This is bad. The simulator doesn't care, but the real world does.

Also, note that his waveforms are NOT 60° apart, but rather 120° apart. Give some thought as to what you actually need.

 

But I don't know can the U1C and U1D be replaced by 2 Nand gate (not schmitt 2 Nand gate)?

With 2-NAND gates it will work just fine.
Not used inputs of chips should be connected to ground.

 

With 2-NAND gates it will work just fine.
Not used inputs of chips should be connected to ground.
View attachment 299661

Thank you so much for replying me !

 

My guess is that he used Schmidt trigger input NAND gates only because he needed that for the oscillator circuit that UA1 is a part of and he just used the other gates for the reset logic.

Any time you design asynchronous logic, you have to carefully analyze it to ensure that it can't produce critical glitches or timing hazards, so it's a very good thing that you are thinking about these things (few people do).

In this case, things should work out okay. All three FFs are clocked with the same signal, so the outputs are going to change at about the same time (but in unknown order) shortly after the clock rising edge. The output of the first and third are being used to reset the second, so there's no concern about race conditions because it doesn't matter which signal gets to the NAND gates first. It also doesn't matter whether there are glitches when the reset is asserted since it doesn't matter if it gets asserted one time or a dozen times.

What needs to be looked at more critically is whether there are any static-0 hazards for the reset signal for the second FF. In other words, is it possible, given that the first FF output might change before the third or it might be the other way around, for there to momentarily be a HI at both inputs of the NAND gate during a state transition that should NOT reset the second FF.

To do that, you need to walk though every possible state change and see what happens under each possibility. In this case, you discover that the reset logic appears to serve no purpose.

But that's an illusion.

This is a six-state Johnson counter, that is intended to cycle through the sequence:

000 -> 100 -> 110 -> 111 -> 011 -> 001 (and repeat)

(These are the values of the Q outputs, notice that his QC is coming from the Qbar of the middle FF).

When the system is running through this sequence, the only time that both inputs to the reset logic are HI are when the first and third FFs are LO (since it's the Qbar outputs from each going to the reset logic). This will force the middle FF to reset to LO, which it already is.

So what does it do?

Well, there are eight possible states and the Johnson counter doesn't use two of them, namely 010 and 101.

What if the circuit powers up in one of those two states?

This would result in a two-stage counter that would go

010 -> 101 (and repeat)

So in either of these states, it will quickly get to 010, which will trigger the reset logic, forcing it to go to 000 and then back into the desired sequence.

The same would hold if a cosmic ray or some other glitch upset one of the FFs and put the circuit into either of these two states.

Do note that, in his simulation, he leave unused inputs floating. This is bad. The simulator doesn't care, but the real world does.

Also, note that his waveforms are NOT 60° apart, but rather 120° apart. Give some thought as to what you actually need.

It's very kiiiiiind of you that you explain this problem in detail.
I learn a lot from your advice! It helps a lot! I should think more when I design a circuit.

I just can't believe that the question is answered by even 3 persons because this issue was dicussed 2years ago and I just register the webset few days ago.
So warm-hearted of you all~
So lucky to meet you all !

 

Are you sure you want 60° phase shift? 3-phase signals are 120° apart..

Thanks for reminding me!
I noted that and changed the circuit.