I am trying to trigger a 555 by first delaying its activity using the RESET pin. I begin by charging a capacitor from 0 v., and apply that value to the RESET pin. Eventually, the RESET pin considers itself as HIGH, and the timer goes about its business. In a simulation, the changeover point seems to be about 2/3 of supply voltage.

I have read several data sheets and can't any explanation of the low/high transition point on the RESET pin. The sheets usually give a specified range for what LOW is, but does not deal with the HIGH transition.

Does anybody out there know at what voltage a 555/556 RESET pin would normally transit to chip in active status? I suppose it is also a function of chip technology.

Thanks in advance for any help with this.

 

All Digital Inputs have a Low Threshold below which Logic is 0; a High Threshold above which Logic is 1. Between the two thresholds is a range that CANNOT be defined as Lo or Hi for the reason, that for a particular voltage in that "grey" area, some samples of the same component may respond to it being HI, others LO.

Ramesh

 

Since the Reset line is connected to the base of a PNP transistor (according to TI's datasheet), a voltage 0.7V above the low voltage level should allow the timer to work. But for best results, use a voltage as close to Vcc as you can.

 

Yep agree with ldc3, the minimum low threshold is 0.7V for reset signal.

 

Using a large cap, 10μF ?, in shunt with reset works for powerup reset, but adding an IC output for reset allows more versitility. Still need a hi value pullup resistor with cap.

 

This site looks useful for hooking up and determining an ideal R and C value.