I am learning about logic gates with the inputs can be one of the 4 value logic(0,1, x, z).
The true table of these gates are listed in attached picture, but there some output that I can't to explain why it is. For example:
With the OR gate in picture, when A is "0" and B is "z" then the output of the gate is "x". But how can I prove this result? I thought that "z" mean disconnect and the output should be "0" but I was wrong.
Could anyone show me how to prove for these results?

 

From my opinion, z is disconnected (it is also known as floating), but it do not mean it's grounded.

Another term 'x' is don't care, meaning either logic '0' or '1'.
(Once this term is put it, it show that the input or output is not that important since it can be change either logic '0' or '1'.)

This shown whatever the input B is, the OUT will give the same state to the input B. (But I rather put 'Q' in this case because some cases like inverter will yield 'Q bar' if the input is 'Q').


Without a proper ground, the output of it will be don't care. This is because there is no reference point for the input if it's disconnected.

 

Without a proper ground, the output of it will be don't care. This is because there is no reference point for the input if it's disconnected.

Thanks for help!
But I am still confused with the case A= "0" and B= "z".
Let say that I have the Diode-Resistor OR Gate in the attached picture below.
Suppose V(high)= 5v for logic 1 and V(low)=0v for logic 0. What should be the voltage value of z high impedance state?
Is the voltage value change between 0 and 5 V?
Z state is used to transmit no logic, is this mean that the voltage value of it cann't 0 or 5 V. And thefore it don't affect to the circuit.
Now if A is "0" and B is "z" can I say that the out is 0 V?

 

Suppose V(high)= 5v for logic 1 and V(low)=0v for logic 0. What should be the voltage value of z high impedance state?
Is the voltage value change between 0 and 5 V?

Not necessary between 0 and 5V, it can sometime have the voltage level, even lower than 0V (from my understanding, it might be due to the current flow).
Suppose the diode can block all the currents from cathode to anode, but there is also a possibility that leakage current case can be occur.

So, I will assume it is a changing voltage value.

Z state is used to transmit no logic, is this mean that the voltage value of it cann't 0 or 5 V. And thefore it don't affect to the circuit.

It will definitely affected your circuit due to its changing voltage level. Imagine if in your circuit, B is opened and let it to be 'z'.
Suddenly the voltage level met the condition of logic 1, so what is your input B?

Now if A is "0" and B is "z" can I say that the out is 0 V?

Not necessary =)
But you definitely can say it's 'don't care' or 'x' as you don't care whatever the voltage level of input B.

 

Sorry that I gave the wrong explanations based on your case.

After re-think back many times your situation while driving, I think you may say it's 0 in the case of Diode-Resistor OR Gate, since it got no current flowing inside the circuit (supposedly it is from my experience).
Another point is, your circuit don't have other voltage source, so it may be '0'.

Normally, the gate are built by using BJT and MOSFET (in my reference books), so it have to be refer to the statement that I make it post#4.

 

I am learning about logic gates with the inputs can be one of the 4 value logic(0,1, x, z).
The true table of these gates are listed in attached picture, but there some output that I can't to explain why it is. For example:
With the OR gate in picture, when A is "0" and B is "z" then the output of the gate is "x". But how can I prove this result? I thought that "z" mean disconnect and the output should be "0" but I was wrong.
Could anyone show me how to prove for these results?

First make sure you understand the difference between 'z' and 'x'. In both cases you don't know what the logic value is, so these are 'unknown' states (which is different than 'don't care' states because a 'don't care' state means it doesn't matter which state it is in, while an 'unknown' state means that, whether it matters or not, we simply don't know. So that's how they are the same. They are different because a 'z' state means that it isn't trying to assert a logic level while an 'x' is trying to assert a logic level (whether we know what it is or not). A 'z' state is 'floating' while an 'x' state is a hard, just unknown, logic state.

So if you connect two signals together (physically connect the wires), if you have a '1' on one wire and a '1' on the other wire, you can pretty safely say that you have a '1' on that node even after they are combined (that doesn't necessarily make this a good thing to do, but there are instances in which this is how you do things, particularly in IC design). But if one wire has a '1' and the other has a '0', then you don't know what the result is when they are combined, hence the result is unknown, or 'x'. On the other hand, if one of the wires is floating (or is the output of a gate that is tristated and has a high impedance output), then if you connect that wire to another wire that is at a logic '1', the result will be a logic '1'. The truth table for a wired (W) connection of two signals is therefore:

W|A|0|1|x|z
B||-|-|-|-
0|-|0|x|x|0
1|-|x|1|x|1
x|-|x|x|x|x
z|-|0|1|x|z

If you have either 'x' or 'z' as in input to a logic gate, then (in general) you don't know how the logic gate is going to treat it. So what you have to do is analyze the output under three assumptions: What if it sees it as a logic 0, what if it sees it as a logic 1, what if it sees it as something in between (sometimes you don't have the information you really need to analyze this state, so you just do the other two and caveat your results by saying that 'x' signifies an unknown, but valid, logic level). For some logic families, a floating input (i.e., a 'z') behaves as if it were in a particular state; for instance, TTL treats floating inputs as a high voltage (logic 1). Other families do not like floating inputs at all, such as most CMOS families.

So for your OR (+) gate, keep in mind that it always tries to assert a logic level, so it will not have 'z' as an output state, only {0,1,x}. If one of the inputs if '1', then the output is '1' regardless of the other input, so it doesn't matter whether you know the value of the other input or not. But one input is '0', then the output is equal to the other input. If one input is unkown, then the only way you know the value of the output is if the other input is a value that makes the first one not matter (i.e., a '1').

+|A|0|1|x|z
B||-|-|-|-
0|-|0|1|x|x
1|-|1|1|1|1
x|-|x|1|x|x
z|-|x|1|x|x

 

Thank you for your detail explanation!
Could you tell me what will happen in these cases:
1. In the case of two signals are connected together(physically connect the wires), if one wire have "1" and the other wire is "0" then you said that the the result is when they are combined is unknown, or 'x'. Can you give me an example in a specific circuit that is simple to understand. I am confused why it doesn't cause a short circuit when we connected "1" and "0" together. And if it have a short circuit can I know the result is "0" or "1"?
2.

For some logic families, a floating input (i.e., a 'z') behaves as if it were in a particular state; for instance, TTL treats floating inputs as a high voltage (logic 1). Other families do not like floating inputs at all, such as most CMOS families.

So for your OR (+) gate, keep in mind that it always tries to assert a logic level, so it will not have 'z' as an output state, only {0,1,x}

In the case of TTL family floating inputs create a high voltage (logic 1) but CMOS families isn't.
For CMOS, why floating input create only {0,1,x} not "z"?
Is your true table for OR gate can be apply for both TTL and CMOS families?
3. For NOT gate (attached picture) to explain for the case when the input is "z" then the output is "x", my teacher said that:
There is a capacitor which is created by NOT gate and the capacitor is connected as in the attached picture.
Assume that at first the input A is in "1" logic therefore the C capacitor is charged to some voltage say Vc. Then A is changed to high impedance "z". At this time A isn't connected to anything and the input of NOT gate is the voltage of capacitor, Vc. But we don't know if the voltage Vc is at "1" or "1" logic, thus the output is unknown.
I think this isn't a good answer. What do you think about it? Could you again explain in this case?

 

Thank you for your detail explanation!
Could you tell me what will happen in these cases:
1. In the case of two signals are connected together(physically connect the wires), if one wire have "1" and the other wire is "0" then you said that the the result is when they are combined is unknown, or 'x'. Can you give me an example in a specific circuit that is simple to understand. I am confused why it doesn't cause a short circuit when we connected "1" and "0" together. And if it have a short circuit can I know the result is "0" or "1"?

No. You have one thing that is trying to force a voltage level that corresponds to a '0' by sourcing or sinking as much current as it has to, within the limits of the amount that it physically can. It is connected to another thing that is trying to force a different voltage level that corresponds to a '1' by sourcing or sinking as much current as it has to, again within it's ability to do so. In general, you simply don't know what the result will be. If one source is stronger than the other, it will win. But if they are about equally strong, they you will end up with something that is somewhere between the two.

2. In the case of TTL family floating inputs create a high voltage (logic 1) but CMOS families isn't. For CMOS, why floating input create only {0,1,x} not "z"?

The output from either family will never be 'z' because they will always be trying to drive a logic level onto the output pin.

A TTL input (input, not output) that is floating (i.e. 'z') will be treated the same as if it where at a high voltage because the circuits used to construct the gate behave that way. In particular, you have to pull a small amount of current from an input in order to get the voltage to go to a low level. Without that current daw, the internal circuitry pulls the input to a high voltage level (though very weakly).

You don't have a similar situation with CMOS and a floating input not only does not establish a valid logic level, but it can result in high current draws within as well as an undefined (i.e., neither '0' nor '1', not just unknown) state on the output. It can even result in enough current to destroy the gate.

Is your true table for OR gate can be apply for both TTL and CMOS families?

Close, but not quite. Remember, in TTL, a 'z' input will behave as though it is a '1' input, while in CMOS a 'z' input will behave, at best, as a 'x' input.

3. For NOT gate (attached picture) to explain for the case when the input is "z" then the output is "x", my teacher said that:
There is a capacitor which is created by NOT gate and the capacitor is connected as in the attached picture.
Assume that at first the input A is in "1" logic therefore the C capacitor is charged to some voltage say Vc. Then A is changed to high impedance "z". At this time A isn't connected to anything and the input of NOT gate is the voltage of capacitor, Vc. But we don't know if the voltage Vc is at "1" or "1" logic, thus the output is unknown.
I think this isn't a good answer. What do you think about it? Could you again explain in this case?

It sounds like this is trying to mix to ideas. If you have a capacitor connected to the input of a gate and set it to a logic level and then disconnect whatever was driving it (i.e., change it to 'z'), then the voltage on the capacitor will hold that value for some amount of time. This is known as dynamic memory. But it won't hold it forever. In fact, it will seldom hold it for more than a fraction of a second. If you are just relying on the unavoidable input capacitance of a logic gate to hold the voltage, forget it. This is designed to be extremely small and the act of disconnecting the driving source will probably be enough make the logic level unknown.

 

It might be useful to note that many simulators use more than four states. Some also have a weak pull up and weak pull down as well as, perhaps, a strong pull up and strong pull down (a strong pull will overcome a weak one, but an active output, including 'x', will overcome either a weak or strong pull). Some also have transient states, such as 'rising' for something that was a '0' and is heading for a '1', but is not there yet, and 'falling' for the reverse. Usually, the idea is to adequately model transient behavior through unknown regions without ever ending up with an 'x' state, because that generally hoses the simulation.

 

Hi anhnha

is very simple:

The logic level of x is not known, may be 1 or 0.
Likewise the logic level of z.

The statement of the OR gate is:
Any logic 1 at any input will result in a logic 1 at its output.

So when an input = 1 output will be = 1, regardless of which are the logic level for x or z.

In such a way that when an input is logic 0 output logic level depends on having x.
If x = 1, output = 1, if x = 0 the output = 0.

As we do not know the logic of z. the output will be = x when the other input is 0, but if logic 1 output will be 1.