This question compares two different ways to implement a four-input CMOS AND gate.
(a) A four-input AND gate can be constructed by three two-input CMOS AND gates. The outputs of two two-input AND gates are connected to the inputs of the third two-input AND gate. Draw the corresponding circuit diagram. How many transistors (both PMOS and NMOS) are required?
(b) Show how you can use only 2-input CMOS NAND and NOR gates to build the four-input AND gate. How many transistors (both PMOS and NMOS) are required? (Hint: Use DeMorgan's theorem.)

I have completed part A.
Im having trouble visualizing how I can do B

 

wouldnt this way be worse? I would think it would use the inverse of 3 nand gates. I dont know why they mention nor gates

 

anyone have any ideas?

 

By DeMorgan's theorem:

\(\overline{\overline{A \cdot B} +\overline{C \cdot D}}=A \cdot B \cdot C \cdot D\)

It's definitely cheaper (by transistor count) than 3 AND gates.

 

thanks that really helped me out

 

thanks that really helped me out

So tell us how many transistors it requires, and how many you saved compared to the 3 AND gates.

 

6 pmos and 6 nmos for a total of 12 for the nand nor circuit
9 pmos and 9 nmos for a total of 18 for the and circuit

 

6 pmos and 6 nmos for a total of 12 for the nand nor circuit
9 pmos and 9 nmos for a total of 18 for the and circuit

Excellent! For extra credit, can you do it with 10 transistors?

 

your really pushing it now

 

your really pushing it now

It's simple. If you can design a 2 input NAND, you can design a 4 input NAND. Then you just need an inverter to make in an AND gate.

 

It's simple. If you can design a 2 input NAND, you can design a 4 input NAND. Then you just need an inverter to make in an AND gate.

something like this

 

something like this

Yep. Very much like that.