Background:
This about one part of a school assignment for my PLTW Digital Electronics class. I have attached the pdf of the assignment, the multisim files, and a video of the circuit sim if anyone is interested. Basically I need make a "Now Serving Display" (like the ones seen at deli counters) from Asynchronous Counters. The circuit should count up to 80, increasing by one on a button press, on two seven segment displays and then stop once it reaches 80. First we must make the circuit on NI Multisim 14.2 on something called PLD mode and then download the code onto an FPGA and test it on the NI Digital MiniSystem (myDAQ, myDigital Protoboard, and the Cmod S6 FPGA Module).
The issue:
For the ones place display (LSB) we have to use the CNTR_4BIN-AS which is the PLD mode equivalent of the 74LS93 IC. Anyway I have the counter connected to a digital clock, and I have an AND gate inputs connected to the QD (Q3) and the QB (Q1) outputs of the counter, and the AND gate output to the R01 (MR1) and R02 (MR2) so that when the counter reaches 10 it resets the counter and the display only goes up to 9. However, when this reset happens, the counter just stops counting despite the clock input still working. Please help me fix the problem.
The video the chip in question: https://drive.google.com/file/d/1Ws_uQ-PyV1XT-qZFzNEZYpNpugz0DUtj/view?usp=sharing
This about one part of a school assignment for my PLTW Digital Electronics class. I have attached the pdf of the assignment, the multisim files, and a video of the circuit sim if anyone is interested. Basically I need make a "Now Serving Display" (like the ones seen at deli counters) from Asynchronous Counters. The circuit should count up to 80, increasing by one on a button press, on two seven segment displays and then stop once it reaches 80. First we must make the circuit on NI Multisim 14.2 on something called PLD mode and then download the code onto an FPGA and test it on the NI Digital MiniSystem (myDAQ, myDigital Protoboard, and the Cmod S6 FPGA Module).
The issue:
For the ones place display (LSB) we have to use the CNTR_4BIN-AS which is the PLD mode equivalent of the 74LS93 IC. Anyway I have the counter connected to a digital clock, and I have an AND gate inputs connected to the QD (Q3) and the QB (Q1) outputs of the counter, and the AND gate output to the R01 (MR1) and R02 (MR2) so that when the counter reaches 10 it resets the counter and the display only goes up to 9. However, when this reset happens, the counter just stops counting despite the clock input still working. Please help me fix the problem.
The video the chip in question: https://drive.google.com/file/d/1Ws_uQ-PyV1XT-qZFzNEZYpNpugz0DUtj/view?usp=sharing
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