Hi everyone-

Attached is an image that contains a problem along with my attempt at it. You'll need to open my attachment to see my problem/my work. It's a JPEG file. Here are the directions written again just in case for this problem:

Given the block diagram for a 3-bit shift-left register, draw the output (Q0,Q1,Q2) as a function of time for the clock, clear, and data-in signals given below.

I realize the drawing may be a tad messed up due to my thick point marker and thick ruler. Please let me know if the drawing is correct or if it needs major changes. If major changes are needed, please advise and I'll correct it and post my new drawing online. Thanks so much for your help!

 

Hi everyone:

Here is another attempt at doing that problem I specified in my last post. It may or may not be more correct. Once again, please advise whether I'm right or wrong. If I'm wrong, it'd be great if a picture could be posted showing the correct diagram. If that's not possible, I'd of course greatly appreciate any written advice on how to draw the diagram. Thanks!!

 

I 'm afraid none of the pictures is correct.

For starters, the "Clear" signal isn't there just for the looks. When it is HIGH, all of the FFs will be held on LOW, no matter what is their input.

It also seems that you don't fully understand the operation of the D-Flip Flop. In short, when its clock goes from LOW to HIGH, its state will become equal to its input.

I suggest you first draw the whole of the first FF output, then all of the second and the go to the third.

Also, please post a larger image. This one is a tad small.

 

Thanks for the help georacer!! I got a friend to explain it to me so now I understand it. It was a little complicated to try and do over the innernet. Thanks though for trying to help!!

 

Can you post the correct answer for the rest of the members and future enquirers?