If you do not want to use a transformer, and will use two isolated 12V power source, then I advise you to use instead of the transistor optocoupler better option. This optocoupler Hcpl-3140. 10k resistor will be very slow off the transistor.

 

If you do not want to use a transformer, and will use two isolated 12V power source, then I advise you to use instead of the transistor optocoupler better option. This optocoupler Hcpl-3140. 10k resistor will be very slow off the transistor.

You do not need a transformer nor a separate power supply. There is a technique called bootstrapping where you can bootstrap the switching of the upper FET. This is commonly used in the switching of H bridges. Here is part of a diagram of something I did some years ago.



Lower FET TR1 is switched normally. Upper FET is controlled via optoisolator. C1 gets charged when TR1 is conducting and then holds the charge when it floats up. So C1 effectively replaces an isolated power supply.

That diagram is part of an H bridge where the FETs conduct alternatively, not simultaneously so TR2 needs to conduct when it is at high voltage. In the case of this thread it should be even easier because both conduct at the same time and are at low level. The instant the lower one conducts the upper one has gate voltage from the regular power supply.

Come to think about it you can probably do without the optoisolator and just use the regular power supply with a diode. When the lower one conducts the upper one will too. When the lower one cuts the upper one goes up and loses gate voltage cutting as well.

 

This should work.



Here you only need to control lower FET TR1 and TR2 takes care of itself. When TR1 is conducting then upper FET TR2 has gate voltage and conducts too. The instant TR1 cuts the S of TR2 rises and the G loses voltage so TR2 cuts too.

ETA: We would need to consider the voltage distribution at switching time and probably add some RC snubbers / voltage dividers.

 

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I'm not sure why, but it seems you deleted the circuit you posted, when you did that action then the several posts will be mess, because lost the connection.

 

Here, all the time trying to use passive inclusion of the upper transistor. Even if you use a resistor of 1kOhm, while off the upper transistor is ~2*3e-9*1e3 = 6e-6 = 6us ( C_gate ~3nF).
Lower transistor closes faster. As a result, almost all the high voltage is applied to the transistor.
As a result, the goal does not achieve it. Maximum voltage equal to the voltage of the two transistors of one.

 

Here, all the time trying to use passive inclusion of the upper transistor. Even if you use a resistor of 1kOhm, while off the upper transistor is ~2*3e-9*1e3 = 6e-6 = 6us ( C_gate ~3nF).
Lower transistor closes faster. As a result, almost all the high voltage is applied to the transistor.
As a result, the goal does not achieve it. Maximum voltage equal to the voltage of the two transistors of one.

As I already said, an RC voltage divider should take care of that. You need to provide that anyway because there is no such thing as both FET switching the same instant no matter how you design it.

For faster switching the 1K Resistor can be combined with an inductance (and even increased in value).

 

If you look closely at my circuit with a transformer, you will see a similar control scheme two gates. I understand that there are no identical electronic components. By this I added 6 Transils (SMAJ188A).
My scheme is fast and these diodes can be opened for a short time.

 

I guess I am missing the advantage of having a transformer which can be eliminated.

At any rate, it seems the OP lost interest and this has become moot.

 

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why you use 2 Opt coupler this is expensive, and also the turn off is slow? you have Rg=0ohm in turn on and when you turn off 10k will be in the picture?

 

why you use 2 Opt coupler this is expensive, and also the turn off is slow? you have Rg=0ohm in turn on and when you turn off 10k will be in the picture?

I have been worked for a industry company used the CMOS IC to design the products about 28 years ago, every logic gate will be putted a RC circuit, the products were used in the factory, the noise was the killer, and then the circuit should be stop the killer and we used the RC to do the filters, so until now I still very sensitive for any R and C, any RC parts in front of cmos ic will be delay the time and slow down the frequency, even only used R still will slow down the frequency.

I tested a 100Ω and 10K in the Vgs of an IRF540, when the frequency closing to 30Khz, the square wave became a little curve, when the frequency upper more to the 40Khz, the curve became more obviously, I remembered that your Vgs had putted three parts, they should be to do the job for delay, but I'm not sure how high the frequency you want to use, so I didn't add any parts in front of Vgs.

The internal capacitance Ciss is the frequency killer, but that was made by factory, so we can't change it, when the input frequency more higher then the affecting will be more obviously.

The optocoupler was one way to do the isolation, if you have any other good methods then you can use it, if you can buy the transformer or design by yourself, they all can be used, because I knew that two ways were depend on your experience to calculate and design, so I didn't mentioned that, but Bordodynov already given you the direction, maybe you can ask him some more about that if you are interested in that.