Hey guys! I am a freshman rn and trying to learn Logisim. So this is the assignment that I have in hand, and I have have added the screenshot of the circuit that I made accordingly. It would mean so much if you can read it and correct me where I am going wrong! Please 
Design a basic 16-bit calculator that has 4 data registers. The calculator can add, subtract, and check for equality that are indicated by the control lines: add, sub, and equal. Furthermore there is an Avg signal that indicates when the average of the sum or difference is desired. To determine which registers to operate on, you are given 4 signals that specify which of the registers are to be used, say w, x, y, and z. The output of results should be stored in a register specified by Ow, Ox, Oy, and Oz. Furthermore assume you have to produce an error signal, Err that indicates either an overflow or underflow. Assume the clock frequency is 1kHz, and the propagation delays for the datapath components is as below:
- Carry Ripple Adder - 1FA delay is 23msec
-Comparator - 50msec
-All basic delays - 3nsec
http://imgur.com/a/oS2Fi
Design a basic 16-bit calculator that has 4 data registers. The calculator can add, subtract, and check for equality that are indicated by the control lines: add, sub, and equal. Furthermore there is an Avg signal that indicates when the average of the sum or difference is desired. To determine which registers to operate on, you are given 4 signals that specify which of the registers are to be used, say w, x, y, and z. The output of results should be stored in a register specified by Ow, Ox, Oy, and Oz. Furthermore assume you have to produce an error signal, Err that indicates either an overflow or underflow. Assume the clock frequency is 1kHz, and the propagation delays for the datapath components is as below:
- Carry Ripple Adder - 1FA delay is 23msec
-Comparator - 50msec
-All basic delays - 3nsec
http://imgur.com/a/oS2Fi
