Hello, I am trying to design a thing I call frequency multiplier (if that's even the correct term) which should output 5 clock pulses from a single button press. I could not find any existing IC that could do this, so I improvised using a combination of monstable and astable multivibrators. My idea is that the button would trigger the monostable which then enables the astable to count for a specified period. This monostable also stabilizes button debounce. The timing of these circuits are set so that the astable would output exactly 5 pulses once the button is pressed. However, I cannot get the exact results I expected. The nmos should be able to turn the astable on/off thru its supply, but the waveform shows that it continues clocking even if the monostable output is low. What am I doing wrong? Also, is this timing sufficient enough to clock logic IC counters with ease or should I adjust the frequency to a much slower rate?

 

If I was going to do this, I'd use an Arduino Nano or Pro Mini.
The Arduino can de-bounce the button and produce any pulsed you need, juts change the code. If you have not used an Arduino before, this could be a good starter project. There are cheap Arduino compatible boards available on Ebay and similar places for under $4.
Going with a programmable device makes changing things a lot easier!

 

Well, that defeats the purpose of digital designing. Programmable MCUs for sure are easier way to do things, but designing at IC level gives me more learnings since it has more constraints.

 

You can do it with two ICs.
Make an astable which output a constant frequency using a 555.
Connect the output to the clock input of a 4017.
Connect your pushbutton to the reset pin.
Connect the 6th output to the /CE pin.
[Edit] I realised I misunderstood the requirement. That would give you 5 pulses on 5 different outputs. You probably want 5 pulse on the same pin,
so connect the 6th output of the 4017 through a transistor to invert it, then to the 555 RESET pin.

 

I tested the circuit, but I am still getting a pulse from 5 different pins. I think the Johnson counter (4017) creates a parallel output; however, I need a serial output. Am I missing something?

 

Here's my intended output if it may help clear things.

 

I tested the circuit, but I am still getting a pulse from 5 different pins. I think the Johnson counter (4017) creates a parallel output; however, I need a serial output. Am I missing something?

For my second attempt, take the 555 output. It should give 5 pulses then stop as output 6 forces the 555 into reset.

 

Hi cor,
Please post your LTS asc file, for the two 555 version.
E

 

Three things.

First. for the 555 astable circuit, the timing capacitor is completely discharged at the beginning of the first half-cycle, so that half-cycle is about 60% longer than the succeeding ones. This is not your main problem, but will make the time it takes to make 5 pulses longer than you think.

Second, it always is a bad idea to enable/disable a 555 by switching its power source. Separate from that, you are doing it with an n-channel FET. For the FET to conduct, the gate must be more positive than the source. The first 555's output pulse is around +3.5 V (*not* 5 V), so that is the gate voltage. You are using the generic FET model in LTS, not a specific part number. With a real FET, the threshold voltage is at least 2 V, so the voltage available to power the astable circuit is around 1 V, not 5 V.

The real problem is that the FET is incorrect. It needs either to be flipped over, but then you would need 7 V on the gate to get 5 V to the 555; or changed to a p-channel FET, but then the polarity of the signal from the first 555 is incorrect. So your basic idea is fine, but this circuit approach will not work.

What will work is driving the U2 Reset input with the U1 output directly. Straight wire, no FET. Note that the first half-cycle still will be longer than the rest.

Another way is the same circuit approach, but replace the two 555's with one CD4093 quad Schmitt trigger NAND gate.

Is the trigger input signal *always* going to be shorter than the monostable period?

ak

 

Please post your LTS asc file, for the two 555 version.

 

Is the trigger input signal *always* going to be shorter than the monostable period?

My first assumption is yes, since I would need a sufficient monostable period to pulsate 5 times. But now that you mentioned it, I realized that there may be an issue with that. The button cannot be pressed multiple times in the duration of the monostable period, as it will only register one 5 pulse, instead of (number of presses) * 5 pulses.

 

I am curious as to how would the CD4093 work for this application. I have never come across Schmidt trigger gates.

 

hi cor,
This is the method I would use.
E

 

Here's a 555 circuit using a CD4017 counter to give one to nine pulses out, depending upon the counter output connection to the 555 (5 pulse connection shown):
It does not depend upon the relative timing of two 555's, and thus guarantees an exact output count independent of any 555 component tolerance timing variations (which can be particularly significant with electrolytic capacitors).

An RC pulse differentiator is added to the trigger input to make the count independent of the trigger pulse width.

I also increased the timing resistor values and reduced the timing capacitor values by a factor of 10, so the 4017 output drive is sufficient to inhibit the 555 oscillations.

There is a delay approximately equal to the 555 pulse low-time before the pulses start (which keeps the first pulse width equal to the rest).
Would that delay be a problem?

 

Here is something I posted last March on another forum. In this circuit, U1 is an oscillator rather than a monostable triggered by a switch, but the idea is the same and it shows one 555 being controlled through its Reset input rather than by switching its power on and off.. The U1 output high period is long enough to let multiple U2 cycles happen.

Note the oscillator circuits. This is an alternate version of an astable circuit, from the CMOS 555 datasheet. It uses 1 fewer resistor and is more simple to calculate, but the output duty cycle is restricted to 50/50. AND - it still has that first-half-cycle-delay issue.

ak

 

I am curious as to how would the CD4093 work for this application. I have never come across Schmidt trigger gates.

Here is another previous post, using Schmitt trigger gates. The 74AC132 is similar to the CD4093 in function (a quad, 2-input, Schmitt trigger NAND gate), but has a lower operating voltage range and a higher output current rating. Neither of those things matter in your application, but note that the pinouts are different.

A single Schmitt trigger gate (NAND or inverter) makes a simple oscillator with 1 R and 1 C, In this circuit, the U1A oscillator enables and disables the U1B oscillator, making a series of beep bursts. Since you do not need a high current output, U1C can be used with U1A to form the monostable.

Again, as with almost all hysteretic oscillators, the first half-cycle out of U1B will be longer than succeeding half-cycles.

ak

 

My first assumption is yes, since I would need a sufficient monostable period to pulsate 5 times. But now that you mentioned it, I realized that there may be an issue with that. The button cannot be pressed multiple times in the duration of the monostable period, as it will only register one 5 pulse, instead of (number of presses) * 5 pulses.

So, which is it? Do you want "(number of presses) * 5 pulses" ?

The way your original circuit works is that all additional button presses during the monostable period are ignored. If you want something different . . .

The most simple change is to turn the monostable into a retriggerable type. If the button is pressed during the timing cycle, the cycle restarts. That is, if you press the button again after three output pulses, you will get a total of 8 output pulses. Actually, 8.5, because the first-half-cycle delay is not repeated since the output oscillator already is running. Also, exactly when the button is re-pressed will affect the total number of output pulses, so the real range is 7.5 to 9.5 pulses. -ish. Such is life with analog timers.

If you want each button press to add exactly 5 more output pulses, that is a digital circuit. There is another thread somewhere about adding 3 seconds to a countdown timer with each button press. Without a microcontroller, it is more difficult than it sounds. There is a way to do this with all analog circuits, but it is complex with a switched-integrator staircase generator.

And, just for grins, there are two ways to eliminate the first-half-cycle delay. One is to add a DC bias to the 555 oscillator timing capacitor, so it is pre-charged up to just below the lower switching threshold voltage. This takes 2 resistors and 1 diode. The other is to replace the oscillator 555 with a CD4060. This is an oscillator plus a 14-bit divider. The oscillator has the same start-up problem, but it is 1/8000th (2^13) of the output first-half-cycle.

ak

 

instead of (number of presses) * 5 pulses.

If you want to do that, then I see no simple way, other than to use a microprocessor.

 

I see no simple way,

Really? I would have thought a geezer like you would have at least one staircase generator in his past. Thankfully, "simple" is a relative concept. One capacitor.

A charged up capacitor that is loaded by a constant-current sink takes a defined and repeatable amount of time to discharge down to the trip point of a comparator. The time is directly proportional to the charge in the capacitor. The comparator output gates the output oscillator.

A constant current source that is controlled by a monostable injects a fixed amount of charge into the capacitor every time the monostable is triggered. This charging current can be significantly higher than the discharge current, making for a short monostable period. This reduces the minimum recovery time between button presses. The amount of charge injected into the cap is equivalent to the discharge time for five oscillator cycles.

Up to some max limit, pressing the button multiple times increases the cap charge in increments of five output cycles for each push. This can be done at any time while the circuit is running.

OK, one capacitor plus some stuff in front of it plus some stuff behind it. Pick pick pick . . .

Update: 2 Schmitt gates for the monostable, 1 transistor (plus some diodes) each for the current source and current sink, one comparator as the comparator, and two gates as the output oscillator plus output polarity corrector. That leaves 1/2 of a dual comparator package unused. It can be done with only a quad opamp plus the transistors, but a single-supply true monostable with opamps takes a lot of passive parts sprinkled around.

Granted, not as simple as two 555's; but it does more than two 555's could dream of.

ak

 

Really? I would have thought a geezer like you would have at least one staircase generator in his past. Thankfully, "simple" is a relative concept. One capacitor.

A charged up capacitor that is loaded by a constant-current sink takes a defined and repeatable amount of time to discharge down to the trip point of a comparator. The time is directly proportional to the charge in the capacitor. The comparator output gates the output oscillator.

A constant current source that is controlled by a monostable injects a fixed amount of charge into the capacitor every time the monostable is triggered. This charging current can be significantly higher than the discharge current, making for a short monostable period. This reduces the minimum recovery time between button presses. The amount of charge injected into the cap is equivalent to the discharge time for five oscillator cycles.

Up to some max limit, pressing the button multiple times increases the cap charge in increments of five output cycles for each push. This can be done at any time while the circuit is running.

OK, one capacitor plus some stuff in front of it plus some stuff behind it. Pick pick pick . . .

Update: 2 Schmitt gates for the monostable, 1 transistor (plus some diodes) each for the current source and current sink, one comparator as the comparator, and two gates as the output oscillator plus output polarity corrector. That leaves 1/2 of a dual comparator package unused. It can be done with only a quad opamp plus the transistors, but a single-supply true monostable with opamps takes a lot of passive parts sprinkled around.

Granted, not as simple as two 555's; but it does more than two 555's could dream of.

ak

Doesn't sound "simple" to me, but I guess our definitions of simple are significantly different.