Need ur help in designing an fsm....

we are assigned to design a Finite State machine that takes an 8 bit asynchronous data as input serially and transfers that data parallely to the output where it can be stored in a register....
In this module, we have to be able to process any 8 bit asynchronous data along with start, stop and parity(even) bits and then each bit are to be send serially as input. that data is to be stored in a register at the output of fsm in parallel form. This is the module given for us.. as we r freshers in this design, we just know the concepts but we are not so familiar in desiging... and we got struck in drawing states for this module only...
the fsm should be generalized...
for example, if a serial input is given like this 0100 1001 , this has to be serially in and has to be parallely stored out..
i shall be very thankful to you if u can reply me the states that are possible in this design.....
Thank you.... vaas

You will get a lot better response if you tell us what you've done, how far you've gotten, etc. Just saying "I need help with ..." is a guaranteed way to get either no response, or responses similar to my first sentence.

--Rich

i will try to do as u said and i try to post the thread with the maximum information that i know....