How can I disable an 80C88 at board/pin level?

I am an (ex-) embedded software engineer with reasonable (but clearly not enough) hardware knowledge.

I have an ZIF socket that I want to piggy-back onto a board-mounted 80C88, so that I can either plug in an external 80C88 CPU, or an 80C88 ICE.

What is the easist way to disable this onboard 80C88 CPU so that it doesn't drive/output anything (Address/Data/Control signals) by cutting/lifting/pulling up or down one or more pins?

I'm not keen on removing the onboard device, as I'd like the option to be able to use it for test purposes.

Any experts out there - your advice will be gratefully received.

Thanks,
David.

The In Circuit Emulator needs to go between the CPU and I/O. In Circuit Debugger will allow you to trace the instructions without removing the IC. Combined with a logic analyzer, that's how I've normally done what you are trying.

Other option would be replace CPU with ZIF, leave standard CPU in ZIF for most work, swap out for ICE CPU while debugging.

Hi Thatoneguy, I'm a little confused by your answer. I have an ICE (not a debugger), which emulates an entire CPU. What do you mean by saying "between the CPU and IO"? I understand your second point, but as I said in my original post, I don't want to remove the onboard CPU, just disable it.

There must be a way to disable the onboard CPU. As one possible scenrio, while I'm not that familar with Max mode, I believe it is designed to allow several CPUs to be connected to the same bus. Isn't there a way in max mode to make the onboard CPU look like a slave?

Still looking for answers please, as to how to disable the onboard CPU.

If I have HOLD held high on reset, will this do what I am trying to achieve?

I have read that HOLD can be used once the CPU is running to tristate address, data and control lines, to allow something like a DMA controller to take over the bus.

Would this work?

If the CPU has an ENABLE or HOLD pin which makes it completely inert, then one could be piggybacked. The manufacturer would have both the ICE and information on use.

I mentioned ICD/Logic Analyzer, as that is how I've worked on systems in your situation.

I am looking at this problem again. Can anyone suggest how to disable a board-mounted 8088, such that another 8088 piggy-backed on top of it can run, without any conflicts?

I'd really welcome specific responses, not general suggestions.

My answer is so simplistic that I must not understand the question.

Cut the power pin of the existing 80C88 in two, leaving enough metal on each side of the cut to solder to. Tack two 1" pieces of solid 22AWG wire on the pin stubs. Solder the ZIF socket pins (all but the power pin) to the existing 80C88 pins. Tack a 1" piece of 22AWG wire on the power pin of the ZIF socket. Use a header shunt (or a SPDT switch) to connect the wire that is tacked to the pin stub on the PCB to either (a) the existing 80C88 power pin stub or, (b) the ZIF socket power pin.

Not pretty, but should work.

ETA: I am by no means an expert, just a Rube Goldberg fan.

Haven't looked at an 8088 spec for 20 years, nor would I, but I will dare to say you could not float all of it's pins. They didn't do that back then. The question is why? Your rom is likely socketed and that can be your access to the system.

#tracecom, you have understood the question but I suspect that driving processor pins H/L with Vcc not connected wouldn't be a good idea.

#GetDeviceInfo, if the device was socketed I wouldn't be asking the question.

Is there anyone out there who knows the 8088/86 or even the 186 who can help please? I'm not looking for general advice, but guidance from someone who is familiar with the CPU family.

If for example I was to tie HOLD high on the first CPU, would there be any bus contention given that it takes a while to assert?

Thanks,
David.

the rom would very likely have a tri state, which could be piggybacked, allowing you to run test code to verify cpu/system activity. You could tri state the multiplexed cpu bus, but not enough of the remaining pins for a cpu piggyback.

Is there anyone out there please?

80186 - has quite a few valid output signals during 'HOLD' which makes it very difficult - or I cannot think of doing it easily.
Even with 8088, you need to check whether the target is in minimum / maximum mode and need to disable/disconnect all the valid outputs during hold states (of the CPU soldered), when you are putting the soldered CPU on hold permanently!
8088 is normally used with an external oscillator, the 8284 (if I remember correctly), so the clock should not be a problem (8284 can drive a bit more!).
It is not stated in the datasheet whether the CPU will be in Hold state during reset, I would think not, as Hold is sampled during some Tcycle, and at some other Tcycle HLDA is granted alongwith release of bus control.
Reset cycle of both CPUs are also not guaranteed to be exactly synchrounous. Stretching the plugged in CPU's reset a bit more should ensure that the CPU will get its data or instructions correctly, as by then the soldered CPU would have entered HOLD, hopefully!