https://www.hackster.io/news/zilog-...the-standalone-z84c00-cpu-family-723594464754
Zilog Calls Time on the Venerable Z80, Discontinues the Standalone Z84C00 CPU Family
Zilog has announced it is halting production of its standalone DIP-packaged Z80 CPU models — a move that could spell trouble for vintage computing enthusiasts looking to build Z80-based systems or repair existing machines with new parts.


It was a good run.
https://forum.allaboutcircuits.com/threads/memio-emulator-for-z80.117003/

 

A v.e.r.y. good run.

ak

 

I never got to meet Federico Faggin, but I met Ted Hoff who was credited with some of Faggin's work when Intel tried to rewrite history.

I worked with Ted Hoff's group to interface a speech recognition system they were building to an Applicon system in the early 1980's.

 

Back when there were parts stores in Dallas I remember seeing someone with a bin full of used Z80 chips for $0.50 each. I can't say I love the old chip but it was one of my first computers (remember the TRS-80)?

 

Back when there were parts stores in Dallas I remember seeing someone with a bin full of used Z80 chips for $0.50 each. I can't say I love the old chip but it was one of my first computers (remember the TRS-80)?

I had a PT job at the old RS store in Downtown Dallas for a while while in HS.

It was here, on the right.

 

RIP Z80... my first homebrew computer c1980/81 was Z80-based, built on 3 wire-wrapped Eurocards with Intel peripherals and 7400 glue...

 

My first was a 6502.

Sorry, boys, but while the Z80 is an old and trusted friend, and created a uP universe big enough for Itty Bitty to step into, it was the best implementation of the second-best uP design.

IMnsHO.

ak

 

My first was a 6502.

Sorry, boys, but while the Z80 is an old and trusted friend, and created a uP universe big enough for Itty Bitty to step into, it was the best implementation of the second-best uP design.

IMnsHO.

ak

Z80 board


If you've ever built a 8080 cpu, the Z80 was bacon wrapped with bacon on a thick bed of bacon.

8080 main and graphics processor boards with sram and eeprom board.

 

I never got to meet Federico Faggin, but I met Ted Hoff who was credited with some of Faggin's work when Intel tried to rewrite history.

I worked with Ted Hoff's group to interface a speech recognition system they were building to an Applicon system in the early 1980's.

That's fascinating first hand history, why not consider posting a bit more about it here?

https://forum.allaboutcircuits.com/threads/electronics-history.200113/#post-1903227

 

I have a little box I stored some older chips in a few years ago (in fact before I came to the US in 2001)



That black one on the right is a Z80 the markings say SL102-1 ZCPU 8400S 8149 W2 PS on the underside it has CPHILAA015LJ.
I think I pulled that Z80 from and old Microprofessor MPF1 sometime in the late 80s.

 

I have (somewhere) some of the early stepping 368DX chips from old Compaq machines we tried to boot early versions of Linux on, it was a buggy nightmare trying to boot early versions of Linux on it because the chip was riddled with 32-bit processing bugs. Swapped it out with a later stepping and boom it ran like a top.

Intel was then and still is today, infamous for horrible chip errata.

 

Intel was then and still is today, infamous for horrible chip errata.

I remember when some of our early milestones when we got silicon back were booting DOS and running Flight Simulator.

 

Somewhere in a box in the attic I still have a working ZX81 with the 'wobbly' 16k extension RAM pack...

 

I have (somewhere) some of the early stepping 368DX chips from old Compaq machines we tried to boot early versions of Linux on

368DX or 386DX?

Coprocessors for the AMD 386DX 40MHz CPU.

 

368DX or 386DX?

Coprocessors for the AMD 386DX 40MHz CPU.

Woops, 386. I don't think the ones we had used had the DX label. 80386-16 might be it. Wish I could find the box they were in.

 

Found a post of mine with photos.
https://forum.allaboutcircuits.com/threads/cores-that-dont-count.179631/post-1655227

One processor (can't remember which one) was the buggy one that didn't like Linux.
https://www.pcjs.org/documents/manuals/intel/80386/

 

One processor (can't remember which one) was the buggy one that didn't like Linux.

That doesn't narrow it down . . .

ak

 

Somewhere in a box in the attic I still have a working ZX81 with the 'wobbly' 16k extension RAM pack...

That little machine was a lot of fun, slow as hell but who cared. I never had one but a good friend at the time did and he and I would sit around the machine as we played around computing prime numbers and other exciting things.

If I recall it had a "fast" mode, where the CPU could run but no screen updates were made, good old Clive, I miss those days!

 

That doesn't narrow it down . . .

ak

No, but it was honest. Looking at the errata sheet link the DX-20 seems to be the bad one.

We didn’t even know this was “a thing” until Michal Necasek ran across this “Inside Track” article in PC Magazine, February 24, 1987, by John C. Dvorak:

80386 Bug Stopper Dept.: If you buy an 80386 machine, card, or chip, make sure you get the B1 revision of the chip or something newer (B2, B3, and so on). There are far too many bugs in the A1 and A2 versions of the chip to be acceptable. Here’s what to look for: On the top line of the chip you’ll see the designation A80386-16. If it says A80386-16ES, then it’s an engineering sample and the vendor is a cheapskate. The samples have the revision number on the top line as A1, A2, or B1. Look no further.

For the rest of you, look at the second line on the chip. If it’s S40344 then you have a B1 chip. S40334 is the A2 revision and S40276 is the A1 revision….

Fortunately, my 80386-B1 CPU is also marked with a “ΣΣ” (double sigma), which is how Intel marked parts that tested safe for 32-bit multiplication. Some 80386 CPUs suffered from a manufacturing defect that could occasionally result in multiplication errors; defective parts that Intel caught were marked with “16 BIT S/W ONLY” instead of the double sigma.

The 80386-16 is a B1 chip with “ΣΣ” (double sigma).

It was still a horror show of bugs that made you love the simplicity of the Z80.

The B1 stepping became available in late 1986. It corrected many of the bugs in earlier versions, but new ones were either introduced or discovered. The best known of these was the widely publicized multiply failure discovered in mid-1987. The B1 stepping is identifiable either by the “B1” mark or by the code “S40343,” “S40344,” or “S40362.” As is the case with the B0 stepping, the B1 revision leaves a binary three in DL after reset. [Again, we would like to see the B0 values independently confirmed. -JP]

IBTS and XBTS Instructions Removed: The Insert Bit String (IBTS) and Extract Bit String (XBTS) instructions were removed from the 80386’s instruction set. It was determined that they took up too much space on the microprocessor and that their functionality could be duplicated with the SHLD and SHRD instructions. The opcodes 0F A6 and 0F A7 now produce invalid opcode faults.
Multiplication Errors: Certain 80386 microprocessors produce erroneous results when performing multiplication. Not all B1 stepping 80386s suffer from this bug. It is aggravated by increases in the processor’s operating frequency, elevations in the ambient temperature, or decreases in the power supply voltage. This failure is extremely pattern sensitive; certain patterns will produce errors readily, while others never will. [See sample program below]
Double Page Faults: The bug that appeared in the B0 stepping regarding page faults that occurred during page faults has been made a permanent feature of the 80386, with one minor change. If a third page fault occurs while the processor is servicing the first two, the 80386 shuts down. [See Intel Errata #18 below]
Disabling Page Translation: The 80386 does not stop translating linear addresses to physical addresses when paging is disabled. Any page-translation entries that are still in the cache will be used, regardless of the setting of PG in CR0. To completely disable paging, flush the TLB by clearing CR3.
Page Translation Affects I/O Addresses: When paging is enabled, the MMU sometimes erroneously translates I/O addresses above 0FFF as well as memory addresses. Coprocessor references (which appear in the I/O space) are also affected. The I/O addresses are translated as though they were linear memory addresses, using the memory translation tables cached in the TLB. If the “linear” I/O address is not in the cache, no translation will take place; only cached entries produce this effect. [See Intel Errata #10 below]
Page Fault Error Codes: Under certain circumstances, the 80386 pushes an incorrect error code onto the page fault handler’s stack. [See Intel Errata #9 below]
Four-Gigabyte Code Segments: If you define a 4Gb code segment (limit = FFFFF, G = 1), the base address of that segment must be dword-aligned, or the 80386 generates a general protection fault (exception 13) when it fetches an instruction from the beginning of the segment. This feature is expected to become permanent.
Wrong Loop Counter: After a REP INS instruction finishes its last iteration, register ECX holds the value FFFFFFFF instead of 0, if the next instruction after the REP INS references memory. [See Intel Errata #11 below]
LSL Instruction and Stack Pointer: If the LSL instruction is followed by an instruction that references the stack, register ESP may become corrupted. [See Intel Errata #14 below]
Not-Present LDT: If a task switch occurs to a Virtual 8086 mode task and the incoming task’s TSS holds a selector to an LDT descriptor that is marked not present, the 80386 generates a not-present fault (exception 11) rather than reporting an invalid TSS fault (exception 10). [See Intel Errata #16 below]
Reading from CR3, TR6, or TR7: If hardware breakpoints are enabled, reading from CR3, TR6, or TR7 may cause spurious debug faults to be reported. It is recommended that you disable breakpoints and then execute the MOV instruction followed by a JMP instruction before reenabling breakpoints.
Privilege Checking a Null Selector: If you perform an LAR, LSL, VERR, or VERw instruction using a null selector (0000 through 0003), the 80386 actually checks the descriptor in slot 0 of the GDT instead of always failing. [See Intel Errata #15 below]
Privilege Checking Bad Selectors: An LAR, LSL, VERR, or VERW instruction that checks an unreachable selector causes the 80386 to hang unless there is a JMP, CALL, or memory-related instruction already in the prefetch queue. An unreachable selector is one that either is beyond the limit of its descriptor table or references a non-existent LDT. The processor will remain hung until it receives an interrupt.
Faulting Floating-Point Instructions: If the second byte of a floating-point instruction is located in the first byte of a page that will cause a page fault (either because it is not present or because of an impending privilege violation), the 80386 hangs. The processor will remain hung until it receives an interrupt. [See Intel Errata #17 below]
The following sample program has been calculated to produce the [aforementioned multiplication] error. An 80386 that fails one or more of these multiply instructions is obviously faulty. However, passing does not guarantee a perfect part. To their credit, Intel agreed to test all 80386s for a limited time and report on their success or failure. Since then, all 80386s have been tested before shipping. Those that fail have been marked “For Sixteen-Bit Software Only.” [To be exact: “16 BIT S/W ONLY” -JP] Those that passed have been marked with a double sigma sign. All 80386s produced after the B1 stepping should be free of this defect.

; Perform various 16-bit and 32-bit multiply operations...

K1 DD 41h ; memory-based constant 1
K2 DD 81h ; memory-based constant 2

MOV EAX,0042E8h ; load EAX with operand
MUL K1 ; EAX = EAX * 41H
CMP EAX,10FCE8h ; check answer
JNE fail ; failure if not equal

MOV EAX,085D00h
MUL K1
CMP EAX,021F9D00h
JNE fail

MOV EAX,042E80000h
MUL K1
CMP EAX,0FCE80000h
JNE fail
CMP EDX,010h
JNE fail

MOV EAX,0417A000h
MUL K2
CMP EAX,0FE7A000h
JNE fail
CMP EDX,0002h
JNE fail

MOV DX,0AB66h
MOV AX,09AE8h
MUL DX
CMP AX,0B070h
JNE fail

MOV DX,0FDF3h
MOV AX,09AE8h
MUL DX
CMP AX,05238h
JNE fail

MOV DX,0B554h
MOV AX,0E8EAh
MUL DX
CMP DX,0A4F9h
JNE fail

MOV DX,0B4C6h
MOV AX,0E8EAh
MUL DX
CMP AX,0ACFCh
JNE fail
CMP DX,0A478h
JNE fail

MOV DX,0B318h
MOV AX,0E8EAh
MUL DX
CMP DX,0A2F1h
JNE fail

MOV DX,0B43Bh
MOV AX,0E8EAh
MUL DX
CMP DX,0A3FAh
JNE fail

 

https://www.electronicdesign.com/bl...80-is-rising-from-the-deadwith-an-on-chip-dac