If one was to use a discrete 'watchdog' IC, which would be better to use as an input, an address line or data bus line?

A circuit I'm looking at has it driven from the CA1 line off a 6821 PIA, but there is nothing in the setup section of the code telling the 6821 how to configure that line. I'm not sure why it works fine in the original but not my copy. I'm tempted to see if I can move the watchdog input from the 6821 to a convenient address or data line. Thoughts?

 

If one was to use a discrete 'watchdog' IC, which would be better to use as an input, an address line or data bus line?

A circuit I'm looking at has it driven from the CA1 line off a 6821 PIA, but there is nothing in the setup section of the code telling the 6821 how to configure that line. I'm not sure why it works fine in the original but not my copy. I'm tempted to see if I can move the watchdog input from the 6821 to a convenient address or data line. Thoughts?

Terrible idea. There are many faults that will still allow address and data lines to continue beating 'up and down' with the processor completely out to lunch.
Which 'watchdog' IC are we talking about? Why can't you figure out what the CA1 line on the 6821 PIA is supposed to be doing.
The best watchdog strategy is to schedule a periodic, non-interrupt level task, to reset the watchdog timer. Also known as 'kicking the dog'.

 

One way That I have seen in the past is a 555 set up with a fixed pulse rate output.
Along these lines.
http://upperbound.com/projects/555-watchdog-timer/

 

Papabravo: Hmm...

I do have an otherwise unused PIA I/O line at my disposal... perhaps if I went like so:

LDA $0C (PIA port A)
EOR #$80 (flip the current state of bit 7)
STA $0C (write the data back to the port)

and package this into a subroutine called at or near the top of the main loop, then feed PA7 into the watchdog circuit?

 

If you are running an old school retro system I would simply forego a watchdog timer.
Watchdogs are like error traps. What do you do when an error is detected?

 

The code DOES have an error trap routine so that part is covered just fine.

This watchdog line feeds into a MAX706 supervisor IC.

I could either reconfigure that for voltage monitoring only (dropping the reset low if the P/S falls out of spec), or I could dump the MAX706 completely and just make use of two currently idle inverters and a RC time constant to pulse the reset line at power-up?

 

According to the datasheet you don't need to use the WDI (Watchdog Input Line) if you don't want to. Just leave it open (disconnected). If it matters to you you can tell the difference between a power fail and a watchdog timeout. I would keep the MAX706, it makes power on something you no longer need to worry about.

 

OK, so if I can just float the WDI line and be done, then since the MAX706 wound up on a different board from the rest of the core logic, all I need to do for now is pull that pin from the 7-pin header between the two boards.

Let's hope it's that easy.

 

Neither address nor data bus are suitable. Use an interrupt pin.

 

Neither address nor data bus are suitable. Use an interrupt pin.

The WDI pin on the MAX706 is an input pin. It is used to "kick the dog". In "theory" you could use any pin that beats up and down for this purpose, As I pointed out there are faults in processor operation that would keep the watchdog from triggering rendering it useless. WDO is an output pin and yes, that pin should go to an interrupt pin.

 

So I did disconnect the watchdog input to the MAX706 and got a slight improvement; the unit no longer repeatedly resets (but still does not run; suspect it's the CPU gone dead after all - and it's unobtainium.)

Moot. the replacement HC11 chosen has an internal watchdog timer, and the watchdog IC was replaced with a DS1225.