Hi guys. Just a quick one (I think), I'm going through some code and some definitions have thrown me a bit.

tPID fooPID; // Declare a PID Data Structure named, fooPID. tPID structure is defined in dsp.h
fractional abcCoefficient[3]__attribute__((space(xmemory))); // find a place to put the data, use
fractional controlHistory[3]__attribute__((space(ymemory))); // large data model in project build options
//fractional kCoeffs[] = {0,0,0}; // declare Kp, Ki and Kd

tPID is a structure defined in the dsp.h file as follows:

typedef struct {
fractional* abcCoefficients; /* Pointer to A, B & C coefficients located in X-space */
/* These coefficients are derived from */
/* the PID gain values - Kp, Ki and Kd */
fractional* controlHistory; /* Pointer to 3 delay-line samples located in Y-space */
/* with the first sample being the most recent */
fractional controlOutput; /* PID Controller Output */
fractional measuredOutput; /* Measured Output sample */
fractional controlReference; /* Reference Input sample */
} tPID;


abdCoefficient and controlHistory are fractional pointer elements of that structure. I just have a couple of questions. Why does the pointer itself need to be fractional, to point to a fractional data type? and secondly, what is xmemory and ymemory, and why is it used here?

Thank you!

 

Why does the pointer itself need to be fractional, to point to a fractional data type?

Exactly. C needs to know what's being pointed to so it can check (at compile time) you're not mixing up pointers to different type of data structures.

what is xmemory and ymemory, and why is it used here?

Ummm... that looks like a dsPIC concept, and I have not used those devices.

 

I see ernie, it would work if the pointer type was not a fractional, however it would throw an error? i guess if you did pointer+1, it would jump one whole fractional data type if i was to point through a fractional array. yeah i have seen x and y memory a few times before, still have no idea of what it means/why you use it.

 

I remember a while ago using freescale chips and I wondered the same thing... they had memories called xram and yram.

I think it is just nomenclature for different memory spaces in order to distinguish between the two. Their address ranges are probably defined in a header file somewhere. Just a speculation... maybe someone with more experience with the device can comment.

 

Gentlemen. It is common in Harvard architectures, of which the dsPIC is an example,to have multiple separate and independent address bus/data bus combinations. the advantage of doing this is so that the processor can run simultaneous memory operations on the "separate" memories. On is called X and the other is called Y. That's all there is to it.

 

thankyou papa