Lets say we have this circuit:

(https://imgur.com/XzkEG90)
tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns

FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns

First I want to check this circuit for hold-time violations. And then I want to calculate the latency.

What exactly is tccq and tpcq of FlipFlops? I understand that tcd+tccp > thold for the hold-time to be not violated. First I would look for the shortest path. This would be from the FF "D" to the FF "F". The tccq of which FF (D or F or both?) do I have to take in consideration?

 

This is the circuit

T_ccp(FF "D") + T_cd(AND) + T_ccp(FF "F") = 3ns > t_hold.
Is this correct?

 

Usually in the data sheet there is a figure defining the various timing quantities.

tpcq is probably the propagation delay from the clock input to the q output.

 

What does "tcd" stand for. That will probably give you the hint you need.

 

t_cd means contamination delay.
I don't understand, what the FlipFlops ("A"-"D") at the beginning are doing and what their purpose are and what theier effects are on timing and most importantly what theier effects are if I wanted to calculate the latency.

If I ignore the FlipFlops at the beginning: t_pd(NOT) + t_pd(AND) + t_pd(OR) + t_pcq("F") + t_setup("F") = 15ns

 

I've never heard it called that before, but rather tp_min.

Here, the tcd is shortest amount of time it can take for the change at an input to propagate to the output in the form of no longer being at the same state that it was and tpd is the maximum time it can take for the outputs to respond. In between those limits the data is unknown (and hence contaminated).