ME- I have hooked up the (As D/S) SPI PINs see PCB5. I have also added an 8MHz XTL xPLL = 32MHz, to the SLAVE, as I read, it needs to be faster than it's MASTER.
JY- You picked up the SPI bus OK and hooked SCK, MOSI, MISO to the correct pins for the hardware MSSP SPI peripheral on the 4431 slave BUT, you can't use the same SS/ (CS/). Each SPI slave must have its own CS/ line or you will get bus contention due to multiple slaves driving MISO.

Me- Are you referring to this line in 4431? Symbol slave_cs = PORTC.6 The SLAVE doesn't have any of it's own SLAVES, so I think this line can be removed?

No, I;m referring to your hand-drawn CS/ wire on the PCB image. That shows that 2 slaves, the AK8963 and the PIC18F4431 MSSP SPI are using the same CS/ line. If the master 4620 is going to communicate via SPI to these two SPI slaves, each needs its own CS/. Only one CS/ can be low at a time.

JT- Yep. If I understand correctly, OSH doesn't support the hardware SPI peripheral in their library functions so you're on your own.

Me- It does have it in the library, but as there were errors, we have been testing this different method. (Perhaps Oshonsoft SPI is ok??) Probably best to carry on this way?

The only one I see is implemented in firmware i.e. bit banging each serial bit instead of using the hardware MSSP SPI peripheral. Either way, using the MSSP hardware peripheral is probably better.

ME- SSPCON SSPM, can you clarify, MASTER or SLAVE?
JT-I am working on the notion that the 4431 is the SPI slave i.e. the 4620 initiates all SPI comms and drives SCK. That makes the 4431 an SPI slave and since there are multiple SPI slaves on the bus, requires that you use a unique SS/ to select the 4431 slave for comms.

ME- The initial idea was to switch the 4431 between MASTER-SLAVE, so some CODE may still be there from that idea. If you spot any I'll remove it and re-post it in #38. So only MASTER slave_cs = PORTD.2 to SLAVE PORTC.6 IN (SS)

One master, many slaves is a better approach. The SPI design provides for multi-master BUT, you have to write your own protocol so that the various masters know when it's OK to grab the bus and start communications and deal with CS/ lines from multiple sources. It ain't worth it IMO.

So, onward but you do have to separate the CS/ shared between those two slaves. It will take another port pin on the 4620.

Have fun!

 

No, I;m referring to your hand-drawn CS/ wire on the PCB image. That shows that 2 slaves, the AK8963 and the PIC18F4431 MSSP SPI are using the same CS/ line. If the master 4620 is going to communicate via SPI to these two SPI slaves, each needs its own CS/. Only one CS/ can be low at a time.
1/
The only one I see is implemented in firmware i.e. bit banging each serial bit instead of using the hardware MSSP SPI peripheral. Either way, using the MSSP hardware peripheral is probably better.
2/
One master, many slaves is a better approach. The SPI design provides for multi-master BUT, you have to write your own protocol so that the various masters know when it's OK to grab the bus and start communications and deal with CS/ lines from multiple sources. It ain't worth it IMO.
3/
So, onward but you do have to separate the CS/ shared between those two slaves. It will take another port pin on the 4620.
4/
Have fun!

Hi JT,
1/ I'm drawing PCB6 at the moment, where the drawn in tracks will be copper, and the 4431-AKAK8963C (Compass) will be removed, as there is only one on each PCB. The 4620 will address all of the SLAVES.

2/ Whatever this is, it's the way it was done before this iteration:
'SPI Config (In Oshonsoft)
Define SPI_SCK_REG = PORTC
Define SPI_SCK_BIT = 3
Define SPI_SDI_REG = PORTC
Define SPI_SDI_BIT = 4
Define SPI_SDO_REG = PORTC
Define SPI_SDO_BIT = 5
Define SPICLOCK_INVERT = 1

3/ OK.

4/Will do
C

 

1) OK, I'm behind on schematics so don't see that but carry on.
2) That's for the software aka firmware bit-banged SPI function if I read the docs correctly so yes, not applicable using the hardware MSSP SPI peripheral.
3)
4) Good!
Post the new schematic when it's complete so we can throw and eye on it for you?

 

1) OK, I'm behind on schematics so don't see that but carry on.
2) That's for the software aka firmware bit-banged SPI function if I read the docs correctly so yes, not applicable using the hardware MSSP SPI peripheral.
3)
4) Good!
Post the new schematic when it's complete so we can throw and eye on it for you?

Hi JT,
1/ Your not behind, as I'm only just making PCB6
2/OK.
4/Will do.
C.

 

Hi,

1/ Do I need a track between both PICs for signalling or anything else, or can all communication be done via the SPI tracks?
EDIt: No reply, so I've added an extra track for signalling. As I'd run out of PINs on the MASTER, I removed an LED.

2/ What decides CPOL CPHA and CLK IDLE?
Can all of the peripherals use the same settings?
C

 

2/ What decides CPOL CPHA and CLK IDLE?
Can all of the peripherals use the same settings?

The slave decides. Sometimes more than one setup will work with a slave - check the datasheet. Hopefully all slaves on the bus can use the same setup but sometimes not. In that case you have to reconfigure the MASTER for each particular slave setup before dropping CE/. I do it with a subroutine for each different setup.
Good luck!

 

The slave decides. Sometimes more than one setup will work with a slave - check the datasheet. Hopefully all slaves on the bus can use the same setup but sometimes not. In that case you have to reconfigure the MASTER for each particular slave setup before dropping CE/. I do it with a subroutine for each different setup.
Good luck!

Hi JT,
It looks like it is a choice, so I'll leave it as it was written so far, and watch out for errors.
Thanks.
C.

 

Hi,
I've re-drawn the PCB.
Here is the PCB and SCH for PCB6.

Any suggestions or errors found would be appreciated, I should etch them 170221

NOTE, The programs need changing to match the changed PIN outs, so only use titles with PCB6 in them.
C.

 

.. Did not find any decoupling capacitors in your schematic.
100 nF and 100 uF may improve reliability.

 

.. Did not find any decoupling capacitors in your schematic.
100 nF and 100 uF may improve reliability.

Hi d,
Thanks for checking. There are 10uF near each regulator, and 100nF also in the SCH.

This will always be run with batteries, is 100uF still recommended?

I'll move the 100nF nearer to the PICs.
C

 

... ideally, the decoupling caps should be directly between Vdd and Vss for each pic. ... maybe 10 uF is enough, a reference recommended using 100 uF.:

... " I think that the rule of thumb used to be every 4 IC's per 100nF. Personally I always decouple even with DC signals. 100nF for high frequency decoupling 100uF for low frequency and acts as a reservoir if at the end of a weedy pc track. The electrolytic at high frequencies can have a relatively high associated inductance hence acts as pretty poor decoupler at higher frequencies."

... from microchip website:
decoupling capacitor discussion

 

... ideally, the decoupling caps should be directly between Vdd and Vss for each pic. ... maybe 10 uF is enough, a reference recommended using 100 uF.:

... " I think that the rule of thumb used to be every 4 IC's per 100nF. Personally I always decouple even with DC signals. 100nF for high frequency decoupling 100uF for low frequency and acts as a reservoir if at the end of a weedy pc track. The electrolytic at high frequencies can have a relatively high associated inductance hence acts as pretty poor decoupler at higher frequencies."

... from microchip website:
decoupling capacitor discussion

Hi d,
I'll use 100uF + 100nf (104?) and place them as close to each PIC as possible.
Thanks, C.

 

Hi d,
I've updated SCH6 and PCB6 in #48.

I notice that you said "electrolytic" in your reply. I have some 100uF ceramic capacitors, are they ok?

C

 

... The short answer is 'No' ... it has to do with the resultant, low impedance to a certain range of frequencies, as well as being a kind of fast response current reservoir, if I understand correctly.
It looks like the idea is to retain the DC voltage component, and allow higher frequencies to pass to ground. Maybe some intrinsic quality of electrolytic capacitors ( a small inductance value? ) does not allow them to pass extremely high frequencies to ground, necessitating the use of the 100 nF ceramic capacitor in parallel.
... Suggest that you specifically use electrolytic capacitors, and note that there should be a polarization mark on the capacitor shell ... usually a 'negative' sign. This -- terminal must be connected to the lower DC voltage, ... circuit ground in this case, while the other terminal is connected to the higher DC voltage.
... Also, be sure that the electrolytics are sufficiently rated for the voltage to be used, with a margin of safety, but that is not going to be an issue in this application.

 

... The short answer is 'No' ... it has to do with the resultant, low impedance to a certain range of frequencies, as well as being a kind of fast response current reservoir, if I understand correctly.
It looks like the idea is to retain the DC voltage component, and allow higher frequencies to pass to ground. Maybe some intrinsic quality of electrolytic capacitors ( a small inductance value? ) does not allow them to pass extremely high frequencies to ground, necessitating the use of the 100 nF ceramic capacitor in parallel.
... Suggest that you specifically use electrolytic capacitors, and note that there should be a polarization mark on the capacitor shell ... usually a 'negative' sign. This -- terminal must be connected to the lower DC voltage, ... circuit ground in this case, while the other terminal is connected to the higher DC voltage.
... Also, be sure that the electrolytics are sufficiently rated for the voltage to be used, with a margin of safety, but that is not going to be an issue in this application.

Hi d,
Ok, I've changed the caps to Electrolytic, and updated #48.
Thanks, C.