Hello every one
In this circuit,
I had to find the value of Rreg &Crec and then calculate ripple Volatage with these conditions:
Rreg+-5%
Crec+-10%
I've calculated Rreg & Crec in this file(I'm not sure if they're true or not.)

My question is how to find Vripple in this case?
(I know these formulas , but the Vripple I found is different from simulation's.

Vripple=I/2fC I=load current
Vripple=V/2RfC V=max of Vrec
R=load resistance )
Can anyone help me?

 

If you look at the Vrec waveform you will see a peak and a valley.
During the valley, the load gets all the current through Reg.
During the peak, the load gets the current as determined by the zener voltage and the zener gets the rest.

Does that help?

 

If you look at the Vrec waveform you will see a peak and a valley.
During the valley, the load gets all the current through Reg.
During the peak, the load gets the current as determined by the zener voltage and the zener gets the rest.

Does that help?

So how I can calculate exact value of Ireg=(Vrec-Vreg)/Rreg while Vrec is changing between the peak and valley, as you said?

 

I assume that you are trying to find the ripple in Vreg?

As long as Vreg does not fall below Vz and the zener diode is modeled as an ideal zener diode, then the rippple voltage is zero.
No calculation required.

 

You say that you had to find values for Rreg and Creg, but to what specification?

 

So how I can calculate exact value of Ireg=(Vrec-Vreg)/Rreg while Vrec is changing between the peak and valley, as you said?

Well call the peak Vpk and the valley Vdip.
Can you see that when Vrec is at Vdip the zener does not conduct if the input voltage is exactly set for zero current through the zener? If the voltage is slightly higher, then RL gets some current and the zener gets the rest.

The current though RL is always gong to be Vz/RL. Can you figure out the rest now?

 

You say that you had to find values for Rreg and Creg, but to what specification?

In order to design this voltage rectifier & regulator .

 

Well call the peak Vpk and the valley Vdip.
Can you see that when Vrec is at Vdip the zener does not conduct if the input voltage is exactly set for zero current through the zener? If the voltage is slightly higher, then RL gets some current and the zener gets the rest.

The current though RL is always gong to be Vz/RL. Can you figure out the rest now?

yes I can. thank you.

 

yes I can. thank you.

Ok so then now you know the two main design points.
The Vrec valley should be somewhat near the zener voltage (but higher due to tolerances) and the valley will determine the minimum zener current, and the peak will determine the max current though the zener.
In this way the load always gets the correct zener voltage which in theory for an ideal zener means it always get the correct voltage. In practice the zener voltage will vary slightly with current but in zener circuits like this that is usually acceptable.

Good luck with it and please come back and post your results when you are done.

 

Ok so then now you know the two main design points.
The Vrec valley should be somewhat near the zener voltage (but higher due to tolerances) and the valley will determine the minimum zener current, and the peak will determine the max current though the zener.
In this way the load always gets the correct zener voltage which in theory for an ideal zener means it always get the correct voltage. In practice the zener voltage will vary slightly with current but in zener circuits like this that is usually acceptable.

Good luck with it and please come back and post your results when you are done.

Thank you. Here's my calculations and results.

 

Thank you. Here's my calculations and results.