People here were kind enough to help me track down a 70-135 MHz VCO problem recently - I have now incorporated all those suggestions and have coupled this to a second stage that uses a low power (1W) RF FET PD5700. The VCO puts out around 100mV and I am hoping to boost this to give 1/4W or so for final delivery of 5W in the 3rd stage (not yet designed).

Note the FET sits on that big footprint on the right and under-side of the board - I am trying to allow space for some heat dissipation in case I can increase the wattage - output is controlled through gate bias voltage.

I have not yet calculated the final source resistor value for matching here and on the output I am using two rather large old-style trim caps.

Here is the schematic and the proposed board - all comments welcome and appreciated !

 

What happened to your varactor diode?

 

What happened to your varactor diode?

Still there - now shown as a 5-25pF capacitor

 

Ahh...just wondering. Well, anyway, I think your circuit is sound. You want to minimize loading on the oscillator by subsequent stages. If this turns out to be a problem, you can add a source follower between the two existing transistors.

Eric

 

Thanks for taking a look, Eric. I had hoped to have as few transistors as possible but the VCO feature meant that the oscillator stage has to go really easy, voltage wise, on the varactor (at least that's what I found when I tried it) - am I being realistic here to expect 5W output in three stages?
Regards
Dick

 

Following Eric's good advice, and not wanting to make yet another defunct board, I've added in a buffer stage to the previous circuit. I haven't done the matching calculations for the coupling capacitors yet but is my general idea OK? See below please:

 

I would move C26 inside of C3 at the output. Also, if you are going to have this board commercially fabricated, you should put in a lot more vias to connect TOP GROUND and BOT GROUND. I only see three vias. I should see up to 50. I also would NOT put thermal reliefs anywhere on the board.

 

One comment on your emitter follower. The idea of using the buffer is that it presents a high impedance to the source driver. Your biasing arrangement for the base, using 680Ω/100Ω presents a low Z to the proceeding source. My only suggestion would be to scale up the divider.

 

Thank you for your advice.


SLK 001 I take your point regarding the need for multiple inter-plane grounding points - as I make my own circuit boards 50 is rather a large number of vias but, thanks, I have added a lot more. Can you please mention your reasoning for the re-positioning of that blocking capacitor? According to my simple logic it should make no difference either way.

MikeLogix Thank you for your incontrovertible point, I'd totally bungled it there!

Back to the soldering iron!

Dick

 

SLK 001 ...Can you please mention your reasoning for the re-positioning of that blocking capacitor? According to my simple logic it should make no difference either way.

The variable cap is part of your output match. C3 is your output coupling cap. It should be the at the output. With it in the position of your schematic, the match inductor is the result of XL14 - XC3 at the frequency. The change will be small, but it will still change. With C3 outside of the match, the match won't be affected by it.

 

Thanks SLK001 - I figured that must be the reasoning.
Dick

 

One comment on your emitter follower. The idea of using the buffer is that it presents a high impedance to the source driver. Your biasing arrangement for the base, using 680Ω/100Ω presents a low Z to the proceeding source. My only suggestion would be to scale up the divider.

This is why I suggested an FET source follower. The BJT may be fine, though, with the right biasing impedance....the proof is in the pudding.

 

Someone once said the Platypus was an animal designed by a committee. I hope this circuit doesn't end up a platypus.

 

This platypus is a tiresome beast.

I find the overall circuit has an acceptable gain but at the cost of producing an unacceptable waveform. At the risk of being boring here is the latest schematic, layout and final board:

After adjusting the four capacitors and running at 125MHz I get this waveform at the output of the oscillator:

and after the buffer I get this:


this form is not much changed through the final FET stage and there is good gain with the RF voltmeter showing 3V+

Any ideas to tame this brute?

 

Woops (how embarrassing) I missed C20 which decouples the oscillator load from the power supply - let me fix that and report any improvement before anybody wastes their time.
Thanks

 

As I said in your last thread, your layout is hideous. Your GROUND signal is relatively high impedance EVERYWHERE! From the voltage regulator, GROUND is a small "island" with only one connection to the bottom GROUND signal. For each component that is connected to GROUND, trace out its path back to true GROUND and you will see what I mean. I'm surprised that your signal looks as clean as it does, but I think that your scope can't really "see" the actual signal.

Also, when you post the bottom side, post it as read from the top. The text will be reversed, but most of us can read a board layout like that. It is also easier to get a feel of the TOP-BOTTOM flow.

 

Decoupling capacitor fixed. Waveform is improved but still appears unstable:


This is at the output - my scope is only rated for 100MHz and this is 125MHz but the RF voltage meter shows 1.1V here.

Can I hope for better stability?

 

SLK001 said: "As I said in your last thread, your layout is hideous. Your GROUND signal is relatively high impedance EVERYWHERE! From the voltage regulator, GROUND is a small "island" with only one connection to the bottom GROUND signal."

Appreciate your input. Maybe I can try whacking in a few more vias at strategic spots - or is this board a basket case in your opinion?
Dick

 

SLK001 - sounds as if you do a lot of this; in an arrangement like this, is the main source of ground impedance the actual vias themselves or is it more the horizontal distance between desired ground-points? From what I remember of waveguides in physics at school, this frequency is too low and the geometry too small for significant standing wave effect - i.e. ~3m wavelength.
Dick

 

...in an arrangement like this, is the main source of ground impedance the actual vias themselves or is it more the horizontal distance between desired ground-points?

It is both. Just estimate the inductance between the ground points. For instance, a via has approx 1.5~2 nH by itself. That's why I suggested more vias. They would be in parallel, so the effective inductance would be reduced by 1/N, where N is the number of vias.

Here is a suggestion to try to salvage your current board. The red lines are 16 gauge solid copper wires soldered from ground to ground. The red rectangles are additional 1000pF bypass caps.