hii everyone.I got the following question as assignment but am not able to understand it fully...
" Design a D-FF using 4:1 Mux as an internal block used for constructing NOR gate, Using structural VHDL code"
Please give an idea how mux could be used for constructing D-ff...and what the question is referring about the NOR gate....

 

I sounds like they want you to set up a MUX so that it would act like a NOR gate. The way you do this I think is to set the inputs of the "NOR" gate to the select bits of the MUX, and then set the other inputs (A0-A3) of the MUX basically to the truth table of a NOR gate.

S0 S1 Y
0 0 A0
0 1 A1
1 0 A2
1 1 A3

Does that make sense?

I don't have enough experience with structural VHDL code to tell you more, but I'm guessing you'll have to use some clock'event structures. I just can't tell you which.