Had a requirement for a set of 24 bit counters, with reset and enables, to generate
a compare signal under 100 nS. So no code could be used or interrupts. Those methods
just too slow. Had to be a HW solution.
Normally one thinks of ASIC/FPGA to do this.
Here is a codeless PSOC design, one chip, that does that in ~ 60 nS. Took 5 minutes to setup in tool
and program part. Cntrs can run > 30 Mhz.
I tried it at 32 bits but ran out of logic fabric (as told by resource window, right side). Note in
resource window all the other resources available I did not use.
Note the compare can be setup for =, >=, >, <, <=.....
Regards, Dana.
a compare signal under 100 nS. So no code could be used or interrupts. Those methods
just too slow. Had to be a HW solution.
Normally one thinks of ASIC/FPGA to do this.
Here is a codeless PSOC design, one chip, that does that in ~ 60 nS. Took 5 minutes to setup in tool
and program part. Cntrs can run > 30 Mhz.
I tried it at 32 bits but ran out of logic fabric (as told by resource window, right side). Note in
resource window all the other resources available I did not use.
Note the compare can be setup for =, >=, >, <, <=.....
Regards, Dana.
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