A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a Verilog program that implements such a system. Compile and verify the functionality of the program with appropriate test cases in your Verilog Test Fixture.

I have attempted the question above but as of now, I am still trying to debug the process, to where the current value is 110, it should not execute 110 + 1, instead, it should assert ALARM = 1 and count should remain the same, i.e. don't care.

Here is my code below.

`timescale 1ns / 1ps

module D2Q2_mod(
    input [2:0] D_IN, //new input
    input CLK,
    output reg [2:0] ALARM = 3'b000,
    output reg [2:0] COUNT = 3'b000
    );

reg [2:0] D_IN_OLD; //previous input
reg [2:0] D_IN_1 = 3'b000;
/*reg [2:0] D_IN_2 = 3'b000;
reg [2:0] D_IN_3 = 3'b000;*/

always @ (posedge CLK)
begin
  
    if (D_IN == 0 && D_IN_OLD == 0 && D_IN_1 == 0) begin
        COUNT = 3'b000;
        ALARM = 3'b000;
    end

    else if ((D_IN > D_IN_OLD) && (D_IN >= D_IN_OLD + 3'b010) && (D_IN <= 3'b110)) begin  //Dr Chua said "D_IN < 6". Is it becos you don't want 6+2=8(OVERFLOW).
        COUNT = COUNT + 1;
    end
  
    else if ((D_IN < D_IN_OLD) && (D_IN_OLD >= D_IN + 3'b010) && (D_IN <= 3'b110)) begin
        COUNT = COUNT + 1;
    end
  
    else if ((D_IN_OLD < D_IN + 3'b010) && (D_IN <= 3'b110)) begin
        COUNT = COUNT;
    end
  
    else if (COUNT == 3'b110) begin
        ALARM = 3'b001;
        COUNT = COUNT;
    end
  
    /*else if (COUNT == 3'b110 && (D_IN_OLD == 3'b111 && D_IN == 000)) begin
        COUNT = COUNT;
        ALARM = 3'b001;
    end*/
  
    if (ALARM == 3'b001 && (D_IN == 0 && D_IN_OLD == 0 && D_IN_1 == 0)) begin
            COUNT = 3'b000;
            ALARM = 3'b000;
    end
  
    D_IN_1 = D_IN_OLD;
    D_IN_OLD = D_IN;
      
end
  
endmodule

May I know what is wrong with my code? Please be patient as this is my first time doing Verilog.

Thank you.

Moderators note : Please use code tags for pieces of code

 

1 What does it do that it should not, or not do that it should?
2 Show any error messages (best with line numbers)
3 Post your code with code-formatting tags (and maybe line-numbers)
4 Name your compiler/simulator

 

Hi JWHassler.

1. The code should:
A: Read in D_IN at every positive clock edge.
B: If current D_IN and previous D_IN has a difference of 2 or more, increase COUNT by 1.
C: If D_IN is 0 for 3 consecutive clock cycles, COUNT should reset to 0.
D: If COUNT is 6, ALARM will be 1, and COUNT will not increase further till reset to 0 by Step C.

<However, my code above, has the COUNT increase continuously regardless of inputs, but it is supposed to stop counting at 6 (or 3'b110).>

2 and 3. No error messages as the code above compiles and simulate.

4. I am using Xilinx 13.1.

Thank you~

 

It would be a lot more easier to read if you wrote it like

else if ((D_IN < D_IN_OLD) && (D_IN_OLD >= D_IN + 2) && (D_IN <= 6)) begin
COUNT = COUNT + 1;
end

Also, why is alarm three bits long when it is supposed to be a single bit?

These two conditions are completely useless and just clutter the code, count will keep its value unless you change it:

else if ((D_IN_OLD < D_IN + 3'b010) && (D_IN <= 3'b110)) begin
COUNT = COUNT;
end

else if (COUNT == 3'b110) begin
ALARM = 3'b001;
COUNT = COUNT;
end

What is D_IN_1 used for?

 

I see. Oh. Verilog reads DEC numbers like BIN when we run the module, right? Hence, you can use '2' and '6' in place of binary digits, which makes everything clearer.

I wrote this code:

else if ((D_IN_OLD < D_IN + 3'b010) && (D_IN <= 3'b110)) begin
COUNT = COUNT;
end

because I wanted to say, if the difference between the current and previous inputs is less than 2, and the new input is less than, including 6, then COUNT is maintained and hence ("COUNT = COUNT"). Am I wrong in this case?

I wrote ALARM as a 3-bit input, because I did not want to make careless mistakes as I am not very familiar with the syntax, and furthermore, I think 3'b001 is the same as 1'b1. Just wondering, may I ask, are they the same (as in is 3'b001 the same as 1'b1?)

Thank you!

 

Like I said, unless you change the COUNT with one of the statements, it will keep its old value anyway, so no need to explicitly write that.
Yes 3'b001 is the same as 1'b1, but my guess is that your assignement requires a single bit output, so assigning a three bit output instead migth rise some questions.

Also I think the mistake is in this part:

else if ((D_IN < D_IN_OLD) && (D_IN_OLD >= D_IN + 3'b010) && (D_IN <= 3'b110)) begin
COUNT = COUNT + 1;
end

and it should be like this

else if ((D_IN < D_IN_OLD) && (D_IN_OLD + 3'b010>= D_IN )) begin
COUNT = COUNT + 1;
end

and also the check for less than six doesnt make much sense here.

 

To kubeek:

I see. Thank you. I initially didn't really understand what you mean so I asked again. Sorry.

You also suggested that I use the following code:

Code:
else if ((D_IN < D_IN_OLD) && (D_IN_OLD + 3'b010>= D_IN )) begin
COUNT = COUNT + 1;
end

However, I don't understand why is it "D_IN_OLD + 3'b010>= D_IN"? This is because, on manipulating this inequality, I had this:

"3'b010 >= D_IN - D_IN_OLD". But if D_IN (new input) is smaller than D_IN_OLD (the previous input), wouldn't there be a problem when the numbers are deducted in the program? This is because you will get a negative number, which may potentially 'confuse' the computer (I think) unless the minus operation is done in 2's complement.

Am I right to say the above?

Thank you.

 

However, I don't understand why is it "D_IN_OLD + 3'b010>= D_IN"? This is because, on manipulating this inequality, I had this:

"3'b010 >= D_IN - D_IN_OLD". But if D_IN (new input) is smaller than D_IN_OLD (the previous input), wouldn't there be a problem when the numbers are deducted in the program? This is because you will get a negative number, which may potentially 'confuse' the computer (I think) unless the minus operation is done in 2's complement.

Am I right to say the above?

Thank you.

Exactly, but because D_IN can never be less than zero you can avoid going below zero when using subtraction by using adition on the other side instead.
Now, I am not entirely sure how will be the addition done and if verilog promotes the result to 4 bits or not, i.e. when D_IN_OLD is 7, will it compare 9 to D_IN or not, but that should be beasy for you to try out.

 

kubeek, thank you for your help. But is it okay if I were to re-visit this thread after 3 weeks, near the end of April? This is because I have 2 other projects due really soon and I need more attention on them as I am struggling with them too. :/

Sorry. Thank you once again for your guidance. I will be back in 3 weeks (near end-April, when my exams will end)!

 

kubeek, thank you for your help. But is it okay if I were to re-visit this thread after 3 weeks, near the end of April?

You´re welcome, no problem with that, I will get a notification when you come back and make a reply.