Verilog Memory Module Expansion problem

Thread Starter

Wai Kwan

Joined May 7, 2019
1
So for an assignment, we were given a base code to modify. We were to create a module using the given modules, to create a memory with the size 128x16 using the memory module 64x8 which uses 4 16x8 modules which then uses 2 16x4 modules.
This is what I have so far.
https://pastebin.com/eUiBGuqJ
I recieved some tips and after researching, I found out that I need to run the 16 bit portion in parallel, and the 128 in sequence. Which is both being done in the previous given modules. I think I have done the parallel portion of it correctly, But I am unable to figure out how to do the Sequential part.
I am pretty much brand new to verilog so this assignment has been very difficult. If someone could explain to me how the sequential part is done It would be greatly appreciated.
this is the test bench I was given and I modified to work with the new module
https://pastebin.com/hic2ucNj
 
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