Hi,

First verilog app I have writen. It is pretty simple assignment, except I cannot get it to work.
Basically 2 inputs, datain [7:0] and a avail, and 2 outputs largest [7:0] and ready.

When avail changes from 0 to 1, largest reg should be reset. Then while avail is 1, any datain should be compared to the largest reg and saved if it is greater than the value in the register. Then once avail becomes 0, ready should become 1.

Anyone have any ideas on what is wrong below? My largest reg is always outputting X's

Thanks,

Rishi

module comp_datapath (input [7:0] datain, input avail, output reg [7:0] largest);
 initial begin
  largest = 0;
 end
 always @(avail, datain) begin
  if (avail) begin  
   if (datain > largest) largest = datain;
  end
 end
endmodule
module comp_controller (input avail, output ready);
 assign ready = avail ? 0 : 1;
endmodule

 

Please post your test bench and I should easily be able to help you! There is a couple of things that could be going wrong here.