I wrote this module using ModelSim/Verilog and it compiles and runs fine, but now I don't know how to write the testbench to go along with it in order to test it.
Here is the module that I wrote:

module BCDecode(BCDinpt, segcntrl);
  input [3:0] BCDinpt;
  output reg[6:0] segcntrl;
  
always @(BCDinpt);
  begin
    case(BCDinpt)
      0: segcntrl = 7'b1111110;
      1: segcntrl = 7'b0110000;
      2: segcntrl = 7'b1101101;
      3: segcntrl = 7'b1111001;
      4: segcntrl = 7'b0110011;
      5: segcntrl = 7'b1011011;
      6: segcntrl = 7'b1011111;
      7: segcntrl = 7'b1110000;
      8: segcntrl = 7'b1111111;
      9: segcntrl = 7'b1111011;
      default: segcntrl = 7'b0000001;
    endcase
endmodule

Here is what I have so far for the testbench:

'timescale 1ns / 1ns
module test_BCD;
  reg [3:0] BCDin;
  wire [6:0] segout;
  
  BCDecode BCDmodule (BCDin, segout);
  initial //Clock generator
    begin
      BCDin = 4'b0000;
      BCDin = 4'b0001;
      BCDin = 4'b0010;
      BCDin = 4'b0011;
      BCDin = 4'b0100;
      BCDin = 4'b0101;
      BCDin = 4'b0110;
      BCDin = 4'b0111;
      BCDin = 4'b1000;
      BCDin = 4'b1001;
    end
    
  initial //Test Stimulus
    begin
      
    end

  initial
  $monitor ($stime, ,BCDin, , segout);
endmodule

I haven't written any testbenches so far, and I'm not really sure what goes in the test stimulus section. Thanks in advance for any guidance I might receive. The only thing that I do know about the test stimulus section is that a for loop is supposed to go in there to make implementation easier.

 

First pass, it looks not too bad to me. Though I am not sure you're allowed to have multiple initial blocks...

Use the initial blocks for just that... initialization!

You can do this two ways. Since your code is simple and the test cases can be enumerated easily, you could do everything in the inital block, as you have. But note that you should use delays! Otherwise your input value will change instantaneously.

Just add #20 for example behind each of those assignments.

Otherwise, you could use the initial block properly and just initialize the inputs to zero. Then use an always block to generate your input signals.

If you spend a few min on google reading some tutorials, you will understand better